Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes

ABSTRACT

In a semiconductor integrated circuit device, testing pads ( 209   b ) using a conductive layer, such as relocation wiring layers ( 205 ) are provided just above or in the neighborhood of terminals like bonding pads ( 202   b ) used only for probe inspection at which bump electrodes ( 208 ) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitdevice (hereinafter also called simply a “semiconductor integratedcircuit”), and specifically to a semiconductor integrated circuit(hereinafter also called simply a “flip-chip type semiconductorintegrated circuit”) in which protruding electrodes (hereinafter alsocalled simply “bump electrodes”) such as solder bumps or the like usedfor circuit substrate mounting are formed on a semiconductor substrate.The present invention relates particularly to a structure of a flip-chiptype semiconductor integrated circuit in which attention has beendirected toward a probe test, and a manufacturing method thereof, andrelates to, for example, a technology effective for application to asystem LSI or the like mixed with a memory and a logical circuit or thelike, and a manufacturing method thereof.

Further, the present invention relates to a semiconductor integratedcircuit wherein protruding electrodes (hereinafter also called simply“bump electrodes”) such as solder bumps or the like for circuitsubstrate implementation are formed on a semiconductor substrate andprogram elements each of which permanently or irreversibly changes thefunction of a predetermined portion of the semiconductor integratedcircuit, are installed thereon.

BACKGROUND ART

The following references are known as examples of references each ofwhich has described a semiconductor integrated circuit having bumpelectrodes used for circuit substrate implementation.

(a) Unexamined Patent Publication Hei 5(1993)-218042, (b) UnexaminedPatent Publication Hei 8(1996)-250498 and (c) U.S. Pat. No. 5,547,740respectively show one basic form of a flip-chip type semiconductorintegrated circuit mentioned in the present specification. Namely, theflip-chip type semiconductor integrated circuit is configured asfollows. For example, relocation wirings are routed from bonding pads ofits chip, bump electrodes respectively connected to the relocationwirings are laid out on the surface of the chip in array form (in areaarray form), and the bump electrodes arranged in area array form areexposed from a surface protection film. It is thus possible to enlargethe interval between the bump electrodes, facilitate substrate mountingthat the bump electrodes are respectively connected to wirings for aprinted circuit board and utilize a low-cost printed circuit board inwhich wiring intervals are wide.

In the flip-chip type semiconductor integrated circuit, the bumpelectrodes are terminals capable of being directly mounted orimplemented on a circuit substrate and are equivalent to externalconnecting terminals such as lead pins or the like for a package. Afterthe bump electrodes are formed and wafer processes are all completed,only the bump electrodes are exposed and the bonding pads are finallycovered with an insulating film or a protection film.

The present inventors have compared the number of the bonding pads inthe semiconductor chip with the number of the external terminals (bumpelectrodes) typified by the lead pins for the package. According to thecomparison, bonding pads used only for probe inspection and bonding padsconnected to power terminals or the like by a technique for a bondingoption are not assigned external terminals dedicated therefor. Thus,when the flip-chip type semiconductor integrated circuit is substitutedfor the semiconductor integrated circuit, a wafer probe test can beperformed through the use of all bonding pads if it is antecedent to theformation of the relocation wirings and bump electrodes. However, it hasbeen found out by the present inventors that there is a fear that when aprobe is brought into direct contact with each bonding pad, the bondingpad is endamaged and a failure in connection to each relocation wiringoccurs.

Techniques for probe testing are not described in the References (a)through (c) at all. The technology of forming under bump metals ormetallurgies on bonding pads after having been subjected to probetesting or inspection, has been described in, for example, (d) MichaelJ. Varnau: “Impact of Wafer Probe Damage on Flip Chip Yields andReliability”, International Electronics and Manufacturing TechnologySymposium (Oct. 23-24, 1996) as a reference in which the relation to theprobe inspection has been described. As to the reference described inthe paragraph (d), however, there is a possibility that when a probe isapplied to one of bonding pads antecedent to a relocation wiringprocess, the surface of the bonding pad will damage and the reliabilityof connection to a relocation wiring layer will be degraded, asdiscussed above by the present inventors. A limitation is imposed on theselection of a relocation wiring material.

Further, the following References are known as to the probe testsperformed in the flip-chip type semiconductor integrated circuit.

(e) The technology of applying a probe to each under bump metal ormetallurgy (UBM) antecedent to the formation of bump electrodes toperform a probe test has been described in U.S. Pat. No. 5,597,737.

(f) A configuration wherein testing pads are provided so as to adjoinunder bump metallurgies and be connected thereto, has been shown inUnexamined Patent Publication No. Hei 8(1996)-64633. The testing padsare respectively provided at the sides of bump electrodes.

(g) Unexamined Patent Publication No. Hei 8(1996)-340029 shows adescription related to the invention wherein portions directly abovebonding pads at which relocation wiring layers are formed, are exposedand testing pads for probe inspection are formed at their exposedportions.

(h) Unexamined Patent Publication No. Hei 8(1996)-29451 shows adescription related to the invention wherein each of pads for probetesting is formed by a relocation wiring layer in the neighborhood ofeach bonding pad.

The present inventors could obtain the following results by furtherdiscussing the technologies described in the References referred toabove.

It has been revealed by the present inventors that the technologydescribed in the paragraph (e) also has the possibility that each undersolder bump metallurgy will be endamaged at a probe tip in a mannersimilar to the technology described in the paragraph (d), and has led todegradation in wettability relative to solder and degradation inreliability of connections to each solder bump electrode due to thedamage of a barrier metal used for the prevention of solder diffusion.

Further, the under bump metallurgies are placed in area array form in amanner similar to the bump electrodes in the technology described in theparagraph (e). In the technology described in the paragraph (f), thetesting pads are also laid out in area array form together with the bumpelectrodes. Therefore, it has been revealed by the present inventorsthat each of the technologies described in the References (e) and (f)has a new problem in that it is difficult to apply a normally-usedcantilever type probe to under bump metallurgies or testing padsarranged in a multiple row, and terminal-dedicated expensive probesdisposed in area array form are additionally required.

It has been found out by the present inventors that the Referencedescribed in the paragraph (g) has a problem in that when the size ofeach bonding pad and the interval between the bonding pads become narrowwith high integration of a semiconductor device, the sizes of thetesting pads and the interval therebetween become also narrow, and thepositioning of each probe and reliable contact thereof fall intodifficulties.

It has been revealed by the present inventors that the technologydescribed in the paragraph (h) has the fear that since the area of eachtesting pad is added to its corresponding relocation wiring layer, thecapacitance of a wiring increases and the electrical characteristic of asemiconductor integrated circuit is degraded.

It has been revealed by the present inventors that each of theReferences described in the paragraphs (f) through (h) is accompanied bya problem that since the testing pads are formed on an inorganicinsulating layer or a metal wiring layer, the surface of each testingpad is hard to deform where a hard metal film such as chromium, nickelor the like is used for the testing pads, and hence the contactabilitywith a probe tip is poor, and an expensive probe whose tip is given goldplating and which has adopted a structure capable of obtaining a widecontact area, is required.

Further, as described as the prior arts in the paragraphs (e) through(h), a problem has been revealed that when the probe is applied to thealready-formed solder bump, the probe is applied to a curved surfacecovered with a thick oxide film under a strong load, whereby the bump isapt to deform and the probe per se is easy to undergo damage.

While the aforementioned References have described the flip-chip typesemiconductor integrated circuit and the testing pads paired with thebump electrodes in this way, they do not show any description orsuggestion that has taken into consideration the fact that the bondingpads used only for probe inspection and the bonding pads or the likeconnected to the power terminals or the like by the technique for thebonding option are not assigned the external terminals like the leadpins dedicated therefor as firstly discussed by the present inventors.Namely, the prior arts do not lead to the provision of the inventiveconcept that focused attention on the testing pads dedicated fortesting, which are used only for probe testing or inspection andunnecessary at the final product stage. The testing pads always exist soas to pair with the bump electrodes. In other words, signals necessaryfor testing are set on the precondition that they are capable of beingtaken from the bump electrodes. Thus, the present inventors haverevealed that if the solder bump electrodes are provided even for signalterminals necessary only for testing, then the number of the bumpelectrodes increases and the layout of the bump electrodes at practicalintervals falls into difficulties from the meaning of mounting thereofto a circuit substrate.

An object of the present invention is to provide a semiconductorintegrated circuit capable of executing a probe test without damage topads antecedent to a relocation wiring process and without an increasein the number of bumps, and a manufacturing method thereof.

Another object of the present invention is to provide a semiconductorintegrated circuit capable of reducing an increase in capacitance ofeach wiring, which is caused by the addition of a testing pad, and amanufacturing method thereof.

A further object of the present invention is to provide a semiconductorintegrated circuit capable of enhancing contactability of a probe witheach of testing pads, and a manufacturing method thereof.

A still further object of the present invention is to provide asemiconductor integrated circuit capable of improving reliability ofconnections to a printed circuit board and reducing substrate mountingcosts because a bump-to-bump interval can be taken wide, and amanufacturing method thereof.

A still further object of the present invention is to provide asemiconductor integrated circuit capable of reducing capacitive loadsdeveloped by metallic wirings for laying out protruding electrodes inarray form.

The present inventors have discussed even a program element togetherwith the flip-chip type semiconductor integrated circuit. In asemiconductor integrated circuit, the program element is used for reliefor the like for substitution of a defective or faulty circuit portionthereof with a redundant circuit. As the program element, a fusecomprised of, for example, a metal film or a polysilicon film is heavilyused and programmed by the melting thereof by irradiation with laserlight. A program relative to the fuse is executed after the completionof a probe test. In this stage, openings for exposing bonding pads andfuses have been defined in a passivation film on the surface of a wafer.For example, the probe test is carried out by using the bonding pad, forexample. The laser light is selectively applied to each fuse in such amanner that the location of a defect is found out upon the probe testand the defective portion is substitutable with a relieving circuit,whereby the program for the fuse is carried out.

An electric fuse is known as another program element. For example, U.S.Pat. No. 5,110,754 has described a technology wherein an antifusecorresponding to a kind of electric fuse is used for defective relief orthe like of a DRAM. The antifuse has a configuration capable of beingprogrammed by dielectric breakdown of an oxide film held in aninsulating state. Further, U.S. Pat. No. 5,742,555 has shown, as anexample of an antifuse, an example in which an oxide film is used toform a capacitor in a p-type well region, and a negative voltage isapplied to a well electrode of the capacitor and a positive voltage isapplied to a plate electrode on the oxide film to thereby bring a gateoxide film into dielectric breakdown. As other references each havingdescribed a semiconductor integrated circuit using an electric fuse,there are known U.S. Pat. No. 5,324,681, etc.

As other program elements, there are known non-volatile storage elementseach capable of reversibly changing a programmed state, such as anelectrically erasable programmable EEPROM, a flash memory, etc. U.S.Pat. No. 5,742,555 has described a DRAM having such a program element.

The present inventors have discussed the mounting program elements inthe flip-chip type semiconductor integrated circuit for the purpose ofdefective relief, mode setting and trimming.

The firstly-discussed program element is a fuse capable of being blownby laser. A fuse (polysilicon fuse) comprised of a polysilicon film isshaped in rectangular form over an element isolating region provided ina well region on a semiconductor substrate. One end of the fuse isconnected to a source region of a selection transistor through metalwirings corresponding to plural layers, whereas the other end thereof isconnected to a ground potential through its corresponding metal wiring.After an interlayer dielectric and a passivation film between the metalwirings corresponding to the plural layers are layered over thepolysilicon fuse, the layered film is etched to define an irradiationwindow for the radiation of laser light and finally an insulating filmhaving a thickness of 0.5 μm to 1 μm is left. When the polysilicon fuseconfigured in this way is blown, the laser light is applied theretothrough the insulating film. For example, the width of the polysiliconfilm, a layout interval, and the width of the irradiation window forapplying the laser light are designed so as to take 2 μm, 5 μm an 10 μmrespectively. Applying He—Ne laser having an intensity of 1.5 μJ and aspot diameter of 6 μm at this time enables the polysilicon fuse to beblown.

It has however been revealed by the present inventors that the systemfor blowing the conventional polysilicon fuse by the radiation of laserlight has the following problems.

The first problem is that the process of defining the window forapplying the laser light therethrough is becoming very difficult. In aso-called system LSI product in which a large-capacity DRAM or the likeis mixed with a high-speed logic circuit and an analog circuit, whichhave recently been progress on rapid market expansion in particular, thelogic circuit needs to have metal wiring layers of five layers or more.Thus, since the thickness of the insulating film from the polysiliconfuse to the top passivation film reaches 5 μm or more, it is technicallydifficult to uniformly effect etching for leaving the insulating film toa thickness of about 0.5 μm at a fuse upper portion on the whole surfaceof the wafer. When the thickness of the insulating film at the fuseupper portion is left 1 μm or more, the incident intensity of laserlight becomes weak and the melting-down or blowing of the fuse becomesinsufficient. When the thickness of the insulating film at the fuseupper portion is thinned to 0.5 μm or less, there is in danger of thesurface of the fuse being exposed depending on variations in thesubsequent process treatment. Thus, the probability of failureoccurrence that non-blown fuses will break, becomes high significantly.

The second problem is that the fuse cannot be blown by the conventionalradiation of laser light from the viewpoint of the system of themanufacturing process in the flip-chip type semiconductor integratedcircuit. In the conventional manufacturing process, a manufacturingprocess executed within a clean room in a wafer state is completed in astage in which the formation of the passivation film for preventingmoisture from entering an upper portion of each metal wiring layer hasbeen completed. Afterwards, the assembly into a package is done afterprobe tests and relief have been carried out, followed by execution ofthe final selection. In the flip-chip type semiconductor integratedcircuit on the other hand, the process from the formation of each metalwiring (relocation wiring) similar to a lead frame to the deposition ofsolder bump electrodes is carried out within the clean room in the waferstate after the formation of the passivation film in order to furtherreduce the manufacturing cost thereof. When the conventional system forblowing the fuse through the radiation of the laser light is applied tothe flip-chip type semiconductor integrated circuit, the deposition andprocessing of each metal wiring for constituting the relocation wringsimilar to the lead frame at the upper portion of each blown fuse areperformed, thereby resulting in unavoidance of degradation inreliability due to the corrosion of the polysilicon fuse and entrance ofmoisture from its corroded portion. Thus, the present inventors havefound out the need for a system capable of electrically performing somekind of program in the flip-chip type semiconductor integrated circuitas an alternative to the system for blowing the fuse by the radiation ofthe laser light.

The third problem resides in that the polysilicon fuse needs arelatively large layout area. One fuse needs a layout area of at least5×10 μm². This becomes a big factor that determines the upper limit ofthe number of fuses.

Next, the present inventors have discussed even the adoption of anelectrically writable and erasable non-volatile storage element as theprogram element. According to it, it has been revealed that when thenumber of the program elements may be low, a chip occupied area taken byperipheral circuits used for electrical writing or the like relativelyincreases and hence area efficiency becomes disadvantageous.

According to the result of discussions, the present inventors have foundout superiority in adoption of the electric fuse such as the antifuse orthe like as the program element for the flip-chip type semiconductorintegrated circuit. At this time, the present inventors have furtherrevealed that since the application of a voltage for dielectricbreakdown to the antifuse is a process necessary only in manufacturingstage of the semiconductor integrated circuit, there is no room toprovide dedicated bump electrodes for the purpose of dielectricbreakdown under such circumstances that a large number of bumpelectrodes must be formed with a great increase in the scale of thesemiconductor integrated circuit. Further, since the state ofstress/distortion developed in the bump electrodes is transferreddirectly to a chip because the bump electrodes are used as terminals forcircuit board mounting in the flip-chip type semiconductor integratedcircuit, the present inventors have recognized the need for theprovision of means for relaxing it.

The present inventors have further discussed a bonding option for theflip-chip type semiconductor integrated circuit from another standpoint.The bonding option is a technique for determining operation modesaccording to, for example, whether each of bonding pads assigned tooperation mode setting electrodes of a semiconductor integrated circuit,for example, should be kept floating or connected to a power terminal.To which lead pin a predetermined bonding pad of a semiconductor chipshould be bonded, may be selected upon assembly in the bonding option.However, the bump electrodes are used as the terminals mounted directlyto the circuit substrate or board in the flip-chip type semiconductorintegrated circuit and correspond to the lead pins for the package.Thus, the execution of the process like the bonding option is no longerphysically impossible after wafer processes are all completed. In orderto change each of bump electrodes to be connected to electrode pads likespecific bonding pads, wiring patterns each extending from the electrodepad like the predetermined bonding pad to its corresponding bumpelectrode must individually be changed. On the other hand, the presentinventors have taken recognition of a need to enable a flip-chip typesemiconductor integrated circuit having completed such wiring patternsonce to be functionally set subsequently with a view toward gainingversatility or usability equivalent to the bonding option.

An object of the present invention is to provide a flip-chip typesemiconductor integrated circuit which does not give rise to degradationin reliability elicited by using a by-laser fusible fuse as a programelement, and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductorintegrated circuit wherein electrodes required to electrically changethe state of a program element employed in a flip-chip typesemiconductor integrated circuit do not limit the number of protrudingelectrodes for other applications.

A further object of the present invention is to provide a semiconductorintegrated circuit capable of relaxing the state of stress/distortiongiven to a semiconductor substrate through protruding electrodes in aflip-chip type semiconductor integrated circuit.

A still further object of the present invention is to provide aflip-chip type semiconductor integrated circuit capable of easilyobtaining versatility equivalent to a bonding option with respect tofunction setting or the like, and a method of manufacturing the same.

A still further object of the present invention is to provide amanufacturing method of efficiently carrying out necessary functionselection and relief accompanied by inspection and a change in the stateof a program element to thereby allow the manufacture of a flip-chiptype semiconductor integrated circuit.

The above, other objects and novel features of the present inventionwill become apparent from the following description of the presentspecification and the accompanying drawings.

DISCLOSURE OF THE INVENTION

Summaries of typical ones of the inventions disclosed in the presentapplication will be described as follows:

<<Probe Test and Flip-chip Type Semiconductor Integrated Circuit>>

[1] In the invention related to a flip-chip type semiconductorintegrated circuit having focused attention on a probe test, testingpads (209 b) each using a conductive layer such as a relocation wiringlayer (205) or an under bump metallurgy layer (207) or the like areprovided just above or in the neighborhood of terminals (202 b) likebonding pads, which are not provided with bump electrodes (208) thereatand are used only for probe testing. Similar testing pads (209 a) may beprovided even with respect to terminals (202 a) like bonding pads atwhich the bump electrodes are provided. The probe test is executed byusing these testing pads or under the combined use of under bumpmetallurgies antecedent to the formation of the bump electrodes togetherwith the testing pads. According to the above, bump electrodes for padsdedicated for probe testing may not be added owing to the use of thetesting pads. Further, the use of testing pads provided in theneighborhood of the terminals like the bonding pads and smaller in sizethan the under bump metallurgies enables a probe test to be executedafter a relocation wiring process.

Further, conductive layers like relocation wirings 205), and testingpads (209 a, 209 b) are formed on an organic insulating layer (204) suchas polyimide or the like. Owing to the provision of the testing pads onthe organic insulating layer low in dielectric constant and easy toincrease its thickness, the capacitance between each of the testing padsand a semiconductor circuit placed therebelow can be reduced. Since themodulus of elasticity of the organic insulating layer is relatively low,the surface of each testing pad is easy to deform and hencecontactability of each probe is enhanced.

An insulating layer (206) is formed on the relocation wiring. An underbump metallurgy and testing pads are formed thereon. Thus, the provisionof each testing pad on the layered insulating layers corresponding tothe two layers placed above and below the relocation wiring makes itpossible to reduce the capacitance between each testing pad and thesemiconductor circuit placed therebelow.

[2] The above will further be explained in detail. The testing pads (209b) are provided exclusively to the bump electrodes (208). Thus, thelayout of the bump electrodes at practical intervals can be facilitatedto the fullest extent from the meaning of the mounting thereof to acircuit substrate. Namely, a semiconductor integrated circuit devicecomprises a semiconductor substrate, a plurality of circuit elementsformed in an element forming layer on the semiconductor substrate, aplurality of terminals (202 a, 202 b) formed on the surface of theelement forming layer and connected to the predetermined circuitelements, a plurality of conductive layers (205) which are respectivelyconnected to first terminals (202 a) corresponding to some terminals ofthe plurality of terminals and extend on the element forming layer,protruding electrodes (208) respectively connected to the conductivelayers, testing pads (209 b) respectively connected to all or some ofsecond terminals (202 b) corresponding to the remaining terminals of theplurality of terminals, and an insulating film (206) which covers thesurfaces of the protruding electrodes and the testing pads so as toexpose the protruding electrodes and the testing pads.

In the above, testing pads (209 a) can be added to the terminals (202 a)each having the protruding electrode (208). A wafer probe test caneasily be carried out using the testing pads (209 a, 209 b) alone.

When the conductive layers are used as relocation wirings (205) forprotruding electrodes with respect to the arrangement of the terminals,the insulating films (204, 206) are disposed above and below each of theconductive layers. The insulating films relax the state ofstress/distortion given to the semiconductor substrate through theprotruding electrodes and testing pads in the flip-chip typesemiconductor integrated circuit. If a film containing an organicmaterial such as a polyimide film, a fluorocarbon resin film, or anelastomer film which contains a silicon or acrylic rubber material, isused as the insulating films in particular, then the film is relativelylow in the modulus of elasticity as compared with an insulating filmsuch as a silicon oxide film or the like, it is suited for therelaxation of the state of stress/distortion.

The testing pads can be placed just above the terminals correspondingthereto. Further, the testing pads can regularly be placed in thecentral portion of the semiconductor substrate, and the protrudingelectrodes can regularly be placed outside the testing padsrespectively. The testing pads can also be extended on its correspondinginsulating film.

[3] A method of manufacturing a semiconductor integrated circuit havinga structure wherein the testing pads are provided exclusively toprotruding electrodes, includes a first step (FIGS. 37 through 40) forconstituting a required circuit in an element forming layer on asemiconductor wafer, forming a plurality of terminals (202 a, 202 b)connected to the predetermined circuit elements on the surface of theelement forming inlayer, and causing a plurality of conductive layers(205) to be respectively connected to first terminals (202 a)corresponding to some of the plurality of terminals and to extend overthe element forming layer, a second step (FIG. 43) for formingprotruding electrodes (208) connected to the conductive layers, a thirdstep (FIG. 41) for connecting testing pads (209 b) to all or some ofsecond terminals (202 b) corresponding to the remaining terminals of theplurality of terminals respectively to form the testing pads, a fourthstep (FIG. 42) for inspecting the required circuit formed in the elementforming layer, a fifth step (S9 in FIG. 58) for performing burn-in, anda sixth step (S8 in FIG. 58) for dicing the wafer.

When testing pads (209 a) are added even to the terminals (202 a) eachhaving the protruding electrode (208), the thirst step results in aprocess for connecting all or some of the second terminals and all orsome of the first terminals respectively to thereby form the testingpads.

Burn-in is performed after the execution of dicing posterior to theformation of protruding electrodes. Alternatively, the protrudingelectrodes are formed after burn-in in reverse and dicing may be carriedout. In the former, burn-in sockets prepared for a BGA (Ball Grid Array)type semiconductor chip in which external connecting electrodes aremapped in area array form, can be used appropriately in a manner similarto the flip-chip type semiconductor integrated circuit. Alternatively,the arrangement of protruding electrodes in area array form is matchedwith the arrangement of the terminals for the existing burn-in sockets,whereby custom-engineered burn-in sockets may not be prepared newly andburn-in in each chip unit can easily be performed. This contributes evento a reduction in test cost. In the latter, the burn-in can also becarried out by using testing pads or testing pads and an under bumpmetallurgy as well as a probe test. Thus, contacting with each socketunder a high temperature makes it possible to prevent the deformation ofprotruding electrodes like solder bump electrodes.

<<Program Element and Flip-chip Type Semiconductor Integrated Circuit>>

[4] In the present invention, a program element (1) like an electricfuse is adopted for a flip-chip type semiconductor integrated circuit.Namely, the semiconductor integrated circuit includes a semiconductorsubstrate (10), a plurality of circuit elements (1, 2) formed in anelement forming layer (semiconductor region, circuit element formingregion including wiring layer and insulating layer) on the semiconductorsubstrate, a plurality of terminals (86, 87, 88, 89) formed on thesurface of the element forming layer and connected to the predeterminedcircuit elements, conductive layers (90) which are connected to thepredetermined terminals (86, 87, 88, 89) and extend on the elementforming layer, and protruding electrodes (93) connected to theconductive layers. At this time, a program element (1) for irreversiblychanging a high-resistance state or a low-resistance state of a currentpath or channel by the development of a predetermined potentialdifference in the current channel is provided as at least one of thecircuit elements. At least one of the terminals is defined as voltageinput terminals (86, 87) for forming the potential difference.

According to the above, elicited degradation in reliability is notdeveloped at all owing to the use of a laser-fusible fuse as the programelement.

When the conductive layers are used as the relocation wirings (205) forthe protruding electrodes with respect to the arrangement of theterminals, insulating films (204, 206), which expose at least theprotruding electrodes and cover the surface thereof, can be placed aboveand below each of the conductive layers. Owing to such insulating films,the state of stress/distortion applied to the semiconductor substratethrough each protruding electrode (209) in the flip-chip typesemiconductor integrated circuit can be relaxed. If a polyimide filmcontaining an organic substance or a film such as elastomer is adoptedas the insulating films in particular, then the film is relatively lowin the modulus of elasticity as compared with an insulating film such assilicon oxide or the like, and hence the film is excellent in therelaxation of the state of stress/distortion.

The semiconductor integrated circuit can further be provided with padelectrodes (90, 90 a) which are respectively connected to the terminalsand exposed from the insulating films. The pad electrodes can be usedfor testing pads or the like provided for the purpose of probe tests.

Some pad electrodes (90 a) in the pad electrodes can be used to applyvoltages for developing a predetermined potential difference in theprogram element. In the case of a circuit configuration in which the padelectrodes (90 a) may be kept floating after the program element hasbeen programmed, protruding electrodes may not be assigned to the padelectrodes (90 a). Thus, the electrodes required to electrically changethe state of the program element employed in the flip-chip typesemiconductor integrated circuit do not limit the number of protrudingelectrodes for other applications. On the other hand, in the case of acircuit configuration in which after the program element has beenprogrammed, the pad electrodes (90 a) must forcedly be set to a groundpotential (Vss) or a source voltage (Vcc), protruding electrodes (93 a)are assigned to the pad electrodes (90 a), and the protruding electrodes(93 a) may be connected to power wrings for the ground potential (Vss)or the source voltage (Vcc) on a wiring board upon substrateimplementation.

When the voltages for developing the predetermined potential differencein the program element are voltages different form operating sourcevoltages employed in a circuit other than the program element, theelectrode for applying the program voltage may be shared between aplurality of program elements.

An electric fuse changed from a high-resistance state to alow-resistance state due to an electrical breakdown can be adopted forthe program element. For example, the current path or channel of theprogram element is charged with an insulating film in thehigh-resistance state, and the insulating film is broken in thelow-resistance state.

The breakdown of the insulating film can be carried out by applying apositive voltage (VDD) to one end of the current channel and applying anegative voltage (Vbb′) to the other end thereof. Thus, the programelement can obtain a high voltage as a predetermined potentialdifference, and an absolute value-based voltage with a circuit's groundvoltage (Vss) as the reference can be limited to a substantially normaloperating voltage. In this case, the negative voltage may commonly besupplied from the protruding electrodes or pad electrodes used forapplication of the predetermined voltages for forming the potentialdifference to each individual program elements. Alternatively, aninternal voltage formed inside a chip, based on a positive voltage (VDD)and a ground voltage (GND) supplied from outside the chip may besupplied to each of the program elements. For example, a high voltage(VCH) or a negative voltage (Vbb′) higher than the VDD is used as theinternal voltage. As to the presence or absence of a program for eachprogram element, the applied voltage on the opposite side of the programelement may be controlled by use of an address signal or the like.

The program element can be used for defective relief. Namely, thesemiconductor integrated circuit has normal circuits each comprised ofthe circuit elements and at least one relieving circuit corresponding toone to be substituted for the defective normal circuit and comprised ofthe circuit elements. The program elements can be adopted for memorymeans (160) for storing relief information for specifying the normalcircuit to be replaced by the corresponding relieving circuit. Forinstance, the normal circuits are memory cells and the relieving circuitis a redundant memory cell. The semiconductor integrated circuit has acomparator (161) which compares the relief information stored by thecorresponding program element and an access address signal of eachmemory cell referred to above and is comprised of the circuit elements,and a selection circuit (106XD) which is capable of selecting theredundant memory cell as an alternative to the selection of the memorycell in response to the coincidence of the comparator and capable ofselecting the corresponding memory cell in response to thenon-coincidence of the comparator and which comprises the circuitelements.

The program elements can be used for the function selection of thesemiconductor integrated circuit. Namely, the program elements can beadopted as means (AF0 through AF2) for storing operation modedesignation information for determining operation modes of thesemiconductor integrated circuit. Thus, the flip-chip type semiconductorintegrated circuit can easily obtain versatility equivalent to a bondingoption in terms of the function selection or operation mode selectioneven after the formation of the protruding electrodes.

The program elements can be adopted as means (AF10 through AF12) forstoring trimming information used for selecting the characteristic of apredetermined circuit incorporated in the semiconductor integratedcircuit. For example, the semiconductor integrated circuit has aresistance type voltage divider (183), and the trimming informationstored in the program element selects a divided voltage produced by theresistance type voltage divider.

[5] A method of manufacturing a semiconductor integrated circuit whereinprogram elements like electric fuses are adopted for a flip-chip typesemiconductor integrated circuit, includes a first step for constitutinga required circuit in an element forming layer on a semiconductor wafer,taking or including at least a program element for irreversibly changinga high-resistance state or a low-resistance state of a current path orchannel by development of a predetermined potential difference in thecurrent channel in the circuit and forming a plurality of terminalsconnected to the circuit on the surface of the element forming layer, asecond step (S7) for forming a plurality of protruding electrodes formounting connections, corresponding to some of the plurality ofterminals, a third step (S5) for testing or inspecting the circuit, afourth step (S6) for replacing a defective or faulty portion with arelieving circuit according to the result of inspection by the thirdstep, a fifth step (S9) for performing burn-in, and a sixth step (S8)for dicing the wafer. Further, the method includes a seventh step (S4)for irreversibly changing the state of each of the program elements tothereby select the function of the circuit. The dielectric breakdowntype electric fuse (1) can be used as the program element.

According to the above, the function selection of the semiconductorintegrated circuit is allowed without using a by-laser fusible fuse asthe program element. Thus, this can contribute to yield enhancement of aflip-chip type semiconductor integrated circuit subjected to thefunction selection and manufactured, and an improvement in reliabilitythereof.

The selection of each function by the program element can be carried outbefore the formation of the protruding electrodes. Namely, the secondstep (S7) is carried out after the seventh step (S4). After theformation of the protruding electrodes, irregularities are formed on thewafer to no small extent. If the function selection is done before theformation of the protruding electrodes, then the contact of a probe witheach pad or terminal for the application of a voltage to the programelement for the function selection is easy and the working efficiency ofthe function selection can be improved.

Contrary to the above, the function selecting (S4) based on the programelement can be performed after the formation of the protrudingelectrodes (S7). In this case, it is necessary to expose electrodes forrespectively applying voltages to the program elements on the surface ofthe semiconductor integrated circuit for the purpose of the functionselection in a manner similar to the protruding electrodes. However,since each individual semiconductor integrated circuits can be stockedin a state in which each wafer process has virtually been finished,except for a process attendant on the function selection, stockmanagement is easy.

In the fourth step (S6) for replacing the defective portion by itscorresponding relieving circuit, the replacement thereof can beperformed while the state of each program element is being irreversiblychanged. At this time, the respective steps for the function selection(S4), inspection (S5) and relief (S6) can be carried out by one-circuitprobing processing. Namely, the third step, fourth step and seventh stepare sequentially performed and respectively include probing processingon the terminals or protruding electrodes as needed. If the protrudingelectrodes are formed (S7) after the respective steps for the functionselection (S4), inspection (S5) and relief (S6), then the contact of aprobe with each pad or terminal for the application of a voltage to eachprogram element is easy and the working efficiency of the inspection andrelief can also be improved as well as that of the function selection.

If the protruding electrodes are formed according to the second stepafter the fifth step (S9) for performing the burn-in (S7), it is thenunnecessary to consider the deformation of each protruding electrodeunder a high-temperature environment, and hence the burn-in can easilybe carried out from its standpoint.

[6] When attention is given to the replacement of a defective portionwith a relieving circuit in a flip-chip type semiconductor integratedcircuit, a method of manufacturing a semiconductor integrated circuitincludes a first step for constituting a required circuit in an elementforming layer on a semiconductor wafer, taking or including at least aprogram element for irreversibly changing a high-resistance state or alow-resistance state of a current path or channel by development of apredetermined potential difference in the current channel in the circuitand forming a plurality of terminals connected to the circuit on thesurface of the element forming layer, a second step (S7) for forming aplurality of protruding electrodes for mounting connections,corresponding to some of the plurality of terminals, a third step (S5)for testing or inspecting the circuit, a fourth step (S6) for replacinga defective or faulty portion with a relieving circuit according to theresult of inspection by the third step, a fifth step (S9) for performingburn-in, and a sixth step (S8) for dicing the wafer. The fourth step(S6) is provided as a step for irreversibly changing the state of eachof the program elements to thereby perform the replacement. In thefourth step, a voltage for developing a predetermined potentialdifference in the current path is applied to a predetermined terminalconnected to the program element, of the plurality of terminals, forexample. The program element is used as the dielectric breakdown typeelectric fuse, for example.

According to the above, the defective relief of the semiconductorintegrated circuit is allowed without using a by-laser fusible fuse asthe program element. Thus, this can contribute to yield enhancement of aflip-chip type semiconductor integrated circuit manufactured under therelief, and an improvement in reliability thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing one example of an antifuse circuitemployed in a semiconductor integrated circuit according to the presentinvention;

FIG. 2 is a vertical cross-sectional view illustrating one example of adevice structure of circuit elements which constitute the antifusecircuit shown in FIG. 1;

FIG. 3 is a plan view depicting one example of the layout of antifuseseach using a substrate gate capacitor;

FIG. 4 is a vertical cross-sectional view showing the state of aninitial manufacturing process used for constituting a selectiontransistor and an antifuse shown in FIG. 2;

FIG. 5 is a vertical cross-sectional view illustrating a nextmanufacturing process following FIG. 4;

FIG. 6 is a vertical cross-sectional view depicting a next manufacturingprocess following FIG. 5;

FIG. 7 is a vertical cross-sectional view showing a next manufacturingprocess following FIG. 6;

FIG. 8 is an explanatory view showing one example of a voltage applyingcondition at a dielectric breakdown operation of the antifuse;

FIG. 9 is a characteristic diagram illustrating one example of a voltagecurrent characteristic at dielectric breakdown of the antifuse;

FIG. 10 is a circuit diagram of an antifuse circuit in which aprotection resistor and a latch-up prevention resistor for a selectiontransistor is added to the configuration of FIG. 1;

FIG. 11 is a vertical cross-sectional view illustrating, by way ofexample, a voltage applying condition and a device sectional structurearound an antifuse at dielectric breakdown of the antifuse in thecircuit shown in FIG. 10;

FIG. 12 is a plan view showing a DRAM chip of a flip-chip type DRAMindicative of another example of a semiconductor integrated circuitaccording to the present invention;

FIG. 13 is a chip plan view illustrating an initial manufacturingprocess used when a flip-chip type DRAM is obtained using the DRAM chipshown in FIG. 12;

FIG. 14 is a chip plan view depicting a next manufacturing processfollowing FIG. 13;

FIG. 15 is a chip plan view showing a next manufacturing processfollowing FIG. 14;

FIG. 16 is a chip plan view illustrating a next manufacturing processfollowing FIG. 15;

FIG. 17 is a vertical cross-sectional view depicting a principal portionof an antifuse circuit employed in the flip-chip type DRAM shown in FIG.12;

FIG. 18 is a functional block diagram of a flip-chip type system LSIaccording to a third example of a semiconductor integrated circuit ofthe present invention;

FIG. 19 is a vertical cross-sectional view showing a device structurefor antifuse circuits, a logic circuit and an external input/outputcircuit shown in FIG. 18;

FIG. 20 is a block diagram illustrating one example of a DRAM 106 builtin the flip-chip type system LSI shown in FIG. 18;

FIG. 21 is a circuit diagram depicting one example of the antifusecircuit corresponding to one bit, which is employed in a relief addressstorage circuit;

FIG. 22 is a circuit diagram showing one example of a relief addressstorage circuit using the antifuse circuit shown in FIG. 21;

FIG. 23 is a timing chart showing one example of operation at the timethat the antifuse undergoes an electrical breakdown;

FIG. 24 is a timing chart illustrating one example of the readingoperation of a detection signal;

FIG. 25 is a vertical cross-sectional view depicting one example of adevice section illustrative of transistors and antifuses shown in FIG.22;

FIG. 26 is a logical circuit diagram showing one example of an addresscomparator;

FIG. 27 is an explanatory view illustrating one example of a bondingoption;

FIG. 28 is a circuit diagram depicting one example illustrative of aninput protection circuit and a first-stage input circuit;

FIG. 29 is a logical circuit diagram showing one example of a bondingoption determination circuit;

FIG. 30 is an explanatory view illustrating the manner in whichoperation modes each settable by a bonding option are kept in order;

FIG. 31 is a block diagram showing a configuration which allows afunction selection equivalent to the bonding option by use of theantifuse circuits;

FIG. 32 is an explanatory view depicting the manner in which operationmodes each settable by antifuses shown in FIG. 31 are kept in order;

FIG. 33 is a circuit diagram showing one example of a trimming settingcircuit having adopted antifuses;

FIG. 34 is a logical circuit diagram illustrating one example of a logicconfiguration of a trimming decoder;

FIG. 35 is a plan view depicting one example of a flip-chip type DRAM;

FIG. 36 is a plan view showing the manner in which part of FIG. 35 isshown in enlarged form and a surface insulating layer is removed toallow routing of relocated wirings to be brought into view;

FIG. 37 is a vertical cross-sectional view illustrating an initial statein a manufacturing process of the flip-chip type DRAM shown in FIG. 35;

FIG. 38 is a vertical cross-sectional view depicting a manufacturingprocess step following FIG. 37;

FIG. 39 is a vertical cross-sectional view showing a manufacturingprocess step following FIG. 38;

FIG. 40 is a vertical cross-sectional view depicting a manufacturingprocess step following FIG. 39;

FIG. 41 is a vertical cross-sectional view showing a manufacturingprocess step following FIG. 40;

FIG. 42 is a vertical cross-sectional view illustrating a manufacturingprocess step following FIG. 41;

FIG. 43 is a vertical cross-sectional view showing a manufacturingprocess step following FIG. 42;

FIG. 44 is an explanatory view illustrating a comparison between thenumber of bonding pads in a 64 Mbits synchronous DRAM chip and thenumber of external terminals in a package;

FIG. 45 is a cross-sectional view showing another structure of arelocated wiring portion in the flip-chip type DRAM;

FIG. 46 is a plan view illustrating another example of a layoutconfiguration of testing pads;

FIG. 47 is a vertical cross-sectional view depicting one example of asection structure in the layout configuration shown in FIG. 46;

FIG. 48 is a vertical cross-sectional view showing a further example ofa section structure of a testing pad;

FIG. 49 is a plan view illustrating a further example of a layoutconfiguration of testing pads;

FIG. 50 is a vertical cross-sectional view showing one example of asection structure in the layout configuration shown in FIG. 49;

FIG. 51 is a plan view illustrating a layout configuration in whichtesting pads are provided only for bonding pads dedicated for probeinspection;

FIG. 52 is a vertical cross-sectional view showing a still furtherstructure of a testing pad;

FIG. 53 is a perspective view illustrating the stage of completion of aconventional wire bonding connecting wafer;

FIG. 54 is a perspective view depicting the state of formation of underbump metallurgies following FIG. 53;

FIG. 55 is a perspective view showing a probe inspection processfollowing FIG. 54;

FIG. 56 is a perspective view illustrating a solder bump electrodeforming process following FIG. 55;

FIG. 57 is a perspective view showing a piece cutting process followingFIG. 56;

FIG. 58 is a flowchart illustrating manufacturing process flowssubsequent to a relocation wring forming process of a flip-chip typesemiconductor integrated circuit according to the present invention inthe form of four types of (a), (b), (c) and (d); and

FIG. 59 is an explanatory view showing chip contacts of a probe and asocket or the like in respective testing processes of probe inspections,burn-in and final tests in the respective manufacturing process flowsshown in FIG. 58.

BEST MODE FOR CARRYING OUT THE INVENTION

<<Antifuse Circuit>>

One example of an antifuse circuit employed in a semiconductorintegrated circuit according to the present invention is shown in FIG.1. In FIG. 1, a circuit element designated at numeral 1 is an antifuseused as a dielectric breakdown type electric fuse indicative of oneexample of a program element. The antifuse 1 comprises a so-calledsubstrate gate capacitor formed in a semiconductor region, which isseparated from another peripheral transistor and to which a substratevoltage Vbb′ is applied. There is provided a selection transistor 2having a source terminal to which a gate capacitance electrode of theantifuse 1 is connected, a drain terminal to which a breakdown voltageVDD is applied, and a gate electrode to which a break control signal Vgis applied. In the antifuse (hereinafter also called a substrate gatecapacitor) defined as the substrate gate capacitor, the breakdownvoltage VDD is applied to the gate capacitance electrode of theantifuse1 through the selection transistor 2 turned on in response to abreak control signal Vg of a high level, for example, and the substratevoltage Vbb′ is applied to the antifuse 1 from the substrate side. Dueto the difference between the potentials applied to both ends of theantifuse 1, an insulating film like a gate insulating film of theantifuse 1 is broken down so that the antifuse 1 is changed from ahigh-resistance state to a low-resistance state.

Although not restricted in particular, when the configuration shown inFIG. 1 is applied to the relief of a defective bit of a memory or thelike, the source of the selection transistor 2 is coupled to a selectionterminal of a selector 3. A corresponding bit Ai of an address signaland an inverted signal AiB thereof at a memory access are inputted tothe selector 3. For example, a logical value of the break signal Vg hasa logical value identical to the inverted signal AiB of the address bitAi. The selector 3 selects and outputs the inverted signal AiB when theinput at the selection terminal is a low level (logical value “0”), andselects and outputs the address bit Ai when the input at the selectionterminal is a high level (logical value “1”). Thus, when the antifuse 1is broken by the break signal Vg (=AiB) of the logical value “1”, theselection terminal of the selector 3 is brought to the logical value“0”, whereby the selector 3 outputs the inverted signal AiB of thecorresponding address bit Ai. When the break signal Vg (=AiB) is of thelogical value “0”, the antifuse 1 is not broken and the selectionterminal of the selector 3 is brought to the logical value “1”, wherebythe selector 3 outputs the corresponding address bit Ai. In other words,when the logical value of the address bit Ai coincides with an invertedlogical value of the logical value of the break signal Vg (=AiB), theoutput of the selector 3 is brought to the logical value “1”.

Owing to the use of one-bit configuration shown in FIG. 1 by pluralbits, the antifuses 1 using the plural bits can be programmed withfaulty or defective addresses to be relieved. Namely, a program for theantifuse 1 is executed with the inverted signal corresponding to eachbit for the defective address to be relieved as the break signal Vg foreach bit. When an access address of a memory having finished the programprocessing of the antifuses is equal to each defective address to berelieved, the outputs of the selectors 3 for the respective bits are allbrought to the logical value “1”. If the access address of theprogrammed memory differs from each defective address to be relievedeven one bit, then the output of at least one selector 3 is brought tothe logical value “0”. Detecting this state by an unillustrated negativeAND gate (NANDGATE: NAND) makes it possible to detect an access relativeto the address to be relieved. Thus, a relieving redundant bit isselected in place of a defective bit.

One example of a section structure of circuit elements, which constitutethe antifuse circuit shown in FIG. 1, is shown in FIG. 2. A secondconduction type (e.g., n-type) deep well region 11 is formed in asurface area of a first conduction type (e.g., p-type) semiconductorsubstrate 10, and a first conduction type shallow well region 13 isformed inside the second conduction type deep well region 11. A fistconduction type shallow well region 12 is formed outside the secondconduction type deep well region 11. A selection transistor 2 comprisedof a second conduction type drain region 18, a second conduction typesource region 19, a gate oxide film 15 and a gate electrode 17, which isseparated by element isolating regions 14, is formed in a surface regionof the first conduction type shallow well region 12. An antifuse 1,which is separated by element isolating regions 14 and comprised of agate capacitance oxide film 16, a gate capacitance electrode 17 and afirst conduction type substrate connecting diffused layer 20, isprovided in a surface region of the first conduction type shallow wellregion 13. The gate capacitance electrode 17 is connected to the secondconduction type source region 19 of the selection transistor 2. Further,a breakdown voltage VDD is applied to the second conduction type drainregion 18 of the selection transistor 2, and the substrate voltage Vbb′is applied to the first conduction type substrate connecting diffusedlayer 20.

Assuming that a gate break-down withstand voltage of the substrate gatecapacitor is given as BVg, and the threshold voltage of the selectiontransistor is given as Vths in the semiconductor device of the presentinvention, the antifuse circuit is set to the following expression underthe condition of break signal Vg>VDD+Vths:

VDD+Vbb′>BVg or preferably

|VDD|˜|Vbb′|>BVg/2.

According to the antifuse 1, the aforementioned problem related to theirradiation of laser light for fusing or blowing the conventional fusecan be solved. Namely, it is not necessary to define an irradiationwindow even when the number of metal wiring layers is five or more.Further, since a change in the state of each fuse is carried out basedon an electrical program, a process system like a flip-chip typesemiconductor integrated circuit in which the details thereof is to bedescribed later, also shows no problem about degradation in reliability.Further, since the substrate gate capacitor can be laid out in the formof 3×3 μm² or less even when a 0.5 μm process technology is used, alayout area can be reduced to ⅕ or less as compared with a laser fusiontype. Further, the present process technology can cope with an increasein the number of fuses.

The layout of the two antifuses 1 is shown in FIG. 3 as a plan layout ofthe antifuses each using a substrate gate capacitor. A pattern 21 forforming a deep n-type well region and a pattern 22 for forming a shallowp-type well region are formed on a p-type semiconductor substrate. Eachof patterns 23 defines an element isolating region outside itsrectangle. Each of patterns 24 comprises, for example, a polysiliconlayer for defining a gate electrode 17 of a selection transistor 2 and agate capacitance electrode 17 of an antifuse 1. Reference numerals 25respectively indicate patterns for forming contact holes, and referencenumerals 26 and 27 respectively indicate patterns for forming firstmetal wiring layers. Reference numerals 31 respectively indicate n-typedrain regions 18 each used for the selection transistor 2, referencenumerals 32 respectively indicate n-type source regions 19, referencenumeral 33 indicates a p-type diffused layer, and reference numeral 34indicates a p-type substrate connecting diffused layer.

Cross-sectional views set every respective manufacturing process stepsfor obtaining the configurations of the selection transistor 2 andantifuse 1 (substrate gate capacitor) shown in FIG. 2 are illustrated inFIGS. 4 through 7.

As shown in FIG. 4, trench-type element isolating regions 14 each havinga depth of 0.3 μm are first formed on a p-type silicon substrate 10having a resistivity of 10 Ωcm. Afterwards, a phosphor (P+) ion havingan acceleration energy of 1000 keV is implanted by a dose of 1×10¹³/cm²by an ion implantation method to thereby form a deep n-type well 11. AB+ ion having an acceleration energy of 350 keV, a born (B+) ion havingan acceleration energy of 150 keV, and a BF₂+ ion having an accelerationenergy of 50 keV are respectively implanted by a dose of 1×10¹²/cm², adose of 2×10¹²/cm² and a dose of 5×10¹²/cm² to thereby form shallowp-type wells 12 and 13. Thereafter, a high-withstand gate oxide film 14having a thickness of 7 nm is grown by a thermal oxidation method at atemperature of 850° C. Further, a 1 μm-thick resist film 42 in whichonly a region for forming a substrate gate capacitor is open, is formedby the normal lithography method. Afterwards, the high-withstand gateoxide film 41 in a region in which the substrate gate capacitor isformed, is removed by a wet etching method.

Next, as shown in FIG. 5, the resist film 42 is removed by an ashingmethod. After cleaning of the silicon substrate, a low-withstand gateoxide film 16 having a thickness of 4.5 nm is grown by the thermaloxidation method at the temperature of 850° C. Simultaneously, cleaningand oxidation are added to form a high-withstand gate oxide film 15increased to a thickness of 8 nm. Afterwards, a gate electrode 17 isformed which comprises a 200-nm thick polysilicon film which isdeposited by a CVD method (Chemical Vapor Deposition) at a temperatureof 600° C. and in which a P+ ion having an acceleration energy of 20 keVis implanted by a dose of 4×10¹⁵/cm², and which is processed by thenormal lithography method. An arsenic (As+) ion having an accelerationenergy of 20 keV is implanted by a dose of 2×10¹⁵/cm² to thereby form ann-type drain region 18 and an n-type source region 19. Further, a B+ ionhaving an acceleration of 10 keV is implanted by a dose of 2×10¹⁵/cm² tothereby form a p-type substrate connecting diffused layer 20.

As shown in FIG. 6, side spacers 43 comprised of an oxide film having athickness of 100 nm, which is deposited by a CVD method using atemperature of 700° C. and processed by an etchback method, is furtherformed, and a Co silicide film 44 having a thickness of 40 nm is grownon the substrate and the gate electrode, followed by deposition of asilicon nitride film 45 having a thickness of 100 nm by a CVD methodusing a temperature of 400° C.

Finally, a 1 μm-thick silicon oxide film 46 deposited by the CVD methodand flattened by a CMP method (Chemical Mechanical Polishing) is formedas shown in FIG. 7. Then contact holes are defined in desired positionsand tungsten (W) plugs 47 embedded therein by the CVD method and theetchback method are formed. Further, an aluminum film having a thicknessof 500 nm is deposited by a sputtering method to thereby form firstmetal wirings 48 processed by the normal lithography method, whereby themanufacture of a principal portion is completed.

A voltage applying condition at a dielectric breakdown operation of theantifuse 1 is shown in FIG. 8 by way of example. A ground potential 0Vis applied to the p-type silicon substrate 10 and the shallow p-typewell region 12 in which the selection transistor exists, and a sourcevoltage 3.3V is applied to the deep n-type well region 11. Further, abreakdown voltage VDD=5V is applied to the n-type drain region 18 of theselection transistor with a substrate voltage Vbb′ of the substrate gatecapacitor=−5V. Afterwards, a voltage pulse of a break signal Vg=6V isapplied to its corresponding gate electrode of the desired selectiontransistor 2 for a time of 1 ms, and a voltage of 10V is effectivelyapplied to the low-withstand gate oxide film 16 of the antifuse 1. Thus,the gate insulating film 16 is broken and the antifuse 1 undergoes anelectrical breakdown.

FIG. 9 shows a voltage-current characteristic at dielectric breakdown ofthe antifuse 1 corresponding to the substrate gate capacitor. The plansizes of the substrate gate capacitor are given as an element isolationinterval of 0.25 μm and a gate width of 0.25 μm. When Vbb′=0V, a gatebreakdown withstand voltage BVg is 9V. Since Vbb′=−5V in the presentembodiment, the breakdown voltage necessary for the gate capacitanceelectrode side is reduced to 3.8V. Thus, if 5V are applied from theselection transistor, then the antifuse can be broken without anyproblem. Although the value of a current flowing through thelow-withstand gate oxide film 16 immediately after the breakdown islimited to 1 mA, the resistance value of the post-breakdown fuse isreduced by 10 digits like about 10 kΩ as compared with thepre-breakdown. Thus, the current driving capacity of the selectiontransistor 2 may be designed so as to take 1 mA or more as a guide.Further, the current driving capacity of a comparison transistor 3connected between a relief determination circuit and the selectiontransistor may be designed so that the resistance value of thepost-breakdown fuse reaches about 10 kΩ as a guide.

An example of an antifuse circuit in which a protection resistor and alatch-up prevention resistor for a selection transistor are added to theconfiguration of FIG. 1, is shown in FIG. 10. In FIG. 10, the selectiontransistor 2 is configured as a p channel transistor, and a protectionresistor 50 and a latch-up prevention resistor 51 for the selectiontransistor 2 are added. While operating sources or power supplies forthe circuit shown in FIG. 10 are manifested as Vbb′ and VDD in thecircuit, the clearly-expressed sources are set separately from powerterminals of other circuits. Operating sources or power supplies forpower nonmanifested-circuits are set as Vcc and Vss. A modedetermination circuit 52, a relief address latch circuit 53, NAND gates54, and level converters 55 are provided as circuits for forming breaksignals Vg. When a program mode for an antifuse 1 is set to the modedetermination circuit 52, based on a mode signal 56 (or mode signal 56or part of address signals), the mode determination circuit 52 causesthe relief address latch circuit 53 to latch address data correspondingto each defective bit. Afterwards, the mode determination circuit 52takes in an address for a fuse to be subjected to dielectric breakdown,which is supplied from the outside, and outputs it to its correspondingNAND gate 54 in bit-correspondence form. Address data are shown in thedrawing as A0 through Ai respectively. When an address outputted fromthe mode determination circuit 52 and an address outputted from therelief address latch circuit coincide with each other with both as ahigh level, the outputs of their corresponding NAND gates 54 arerespectively brought to a low level. The output of each NAND gate 54 isconverted to the amplitude of the source voltage VDD by itscorresponding level converter S5. The converted signal is supplied tothe gate electrode of its corresponding selection transistor 2 as thebreak signal Vg. The break signal Vg is brought to a low level inresponse to the low level (logical value “0”) of the corresponding NANDgate 54, whereby a breakdown voltage VDD is applied to its correspondingantifuse 1 used as a substrate gate capacitor. Thus, the antifuse 1undergoes an electrical breakdown.

Although not restricted in particular, the source voltage VDD and thesubstrate bias voltage Vbb′ are respectively set to Vcc and Vss afterthe antifuse 1 has been programmed.

From the above, the corresponding address bit Ai at the time that thefuse 1 undergoes the electrical breakdown, is of a high level (logicalvalue “0”). This relationship is identical to the case shown in FIG. 1.In FIG. 10, a selector 3 is provided at the drain of each selectiontransistor 2 in a manner similar to FIG. 1. A relief determiningoperation at the normal operation subsequent to the antifuse 1 beingprogrammed is identical to the contents described in FIG. 1. Namely,when access addresses of memories having finished the program processingof the antifuses 1 are respectively equal to the defective or faultyaddresses A0 through Ai to be relieved, the outputs of the selectors 3corresponding to the respective bits are all brought to the logicalvalue “1”, whereby accesses relative to the addresses to be relieved aredetected.

A voltage applying condition and a device sectional structure around anantifuse at dielectric breakdown of the antifuse in the circuit shown inFIG. 10 are illustrated in FIG. 11 by way of example. In FIG. 11, a deepn-type well region 61 and a shallow n-type well region 62 are formed ona p-type silicon substrate 60. Shallow p-type well regions 63 and 71 aredisposed in the deep n-type well region 61. A selection transistor 2,which is separated by element isolating regions 64 and comprises ap-type drain region 68, a p-type source region 69, a gate oxide film 65and a gate electrode 67, is formed within the shallow n-type well region62. A substrate gate capacitance oxide film 66 is formed within theshallow p-type well region 63. A substrate gate capacitor, i.e., anantifuse 1 comprises a p-type substrate connecting diffused layer 70 anda gate electrode 67. A protection resistor 50 in which p-type resistancediffused layers 70 are connected using the shallow p-type well region71, is formed between the gate electrode 67 of the substrate gatecapacitor and the p-type source region 69 of the selection transistor 2.

In FIG. 11, the p-type silicon substrate 60 is fixed to a groundpotential Vss (=0V), and Vnw=VDD=5V is applied to the shallow n-typewell region 61 and the shallow n-type well region 62. After Vbb′=−5V isapplied to the p-type substrate connecting diffused layer 70 of theantifuse 1 and the breakdown voltage VDD=5V is applied to the p-typedrain region 68 of the selection transistor 2, the break signal Vg=5Voutputted from the corresponding level converter 55 shown in FIG. 10 isinputted to the gate electrode 67. Thus, Vb′=−5V is applied to onecapacitance electrode of the antifuse 1 and VDD=5V is applied to theother capacitance electrode, so that the substrate gate capacitanceoxide film 66 is brought into dielectric breakdown.

In the example illustrated in FIG. 11, the thickness of the oxide film46 of the antifuse 1 is set as 4.5 nm and formed thinner than that ofthe gate oxide film 65 with a view toward facilitating its dielectricbreakdown. Even in the case where the thickness of the gate oxide filmemployed in the normal DRAM process is 7 nm, its gate breakdownwithstand voltage is about 11V. Therefore, if Vbb′=−7V is applied to thep-type substrate connecting diffused layer 50 of the antifuse 1 evenwhen the thickness of the oxide film 66 of the antifuse 1 is set to 7 nmin a manner similar to the gate oxide film 65, a similar dielectricbreakdown operation is allowed.

<<Flip-chip Type DRAM>>

A DRAM chip for a DRAM (hereinafter called also simply a “flip-chip typeDRAM”) of a flip-chip type indicative of another example of asemiconductor integrated circuit according to the present invention isshown in FIG. 12. In a DRAM chip 80 shown in the same drawing, antifusecircuits are used to relieve faulty or defective bits.

Although not restricted in particular, the DRAM chip 80 has 64 Mbitmemory arrays 84 corresponding to four blocks, which are provided on asemiconductor substrate. Further, the DRAM chip 80 has X decoders (rowdecoders) 83 set every pairs of memory arrays 82, and peripheralcircuits such as Y decoders (column decoders) and main amplifiers 84 setevery memory blocks 82. Antifuse circuits 85 each comprised of anantifuse 1 used as a substrate gate capacitor are provided inassociation with the respective memory arrays 82. Power pads 86 and 87for the antifuse circuits 85 are disposed in the central portion of thesemiconductor substrate. 80×80 μm² metal pads 88 for probe testing areprovided outside the power pads. Further, 40×40 μm² metal pads 89 fortaking or pulling out relocation wirings (lead wires) to bump electrodesare provided. The antifuse circuits 85 can adopt the antifuse circuitsshown in FIGS. 1 and 10 respectively. A program mode is set based on amode signal or the like in the same manner as described above. Theantifuse circuit may enter the program mode by use of a WCBR (forenabling a write enable signal WE and a column-address-strobe signal CASprior to a row-address-strobe signal RAS being enabled) test mode andpart of address signals in a DRAM.

The power pad 86 is a power pad to which a breakdown voltage VDD (=5V)is applied upon breakdown of the antifuse 1 and a source voltage Vcc(=3.3V) is applied upon the normal operation. Upon breakdown of theantifuse 1 (substrate gate capacitor), the other power pad 87 issupplied with its substrate voltage Vbb′ (=−5V) and is fixed to a groundpotential Vss (=0V) upon the normal operation.

FIGS. 13 through 16 are respectively chip plan views showing requiredprocess steps up to the acquisition of a flip-chip type DRAM by use ofthe DRAM chip 80.

First of all, relocation wirings (lead wires) 90 illustrated in FIG. 13by way of example are patterned on the wafer-shaped DRAM chip shown inFIG. 12. Namely, a third layer aluminum wring is formed on the DRAM chip80 shown in FIG. 12, and a passivation film comprised of a 0.5 μm-thickoxide film and a 1 μm-thick plasma nitride film is formed over the thirdaluminum wiring. A photosensitive polymer membrane or film having athickness of 10 μm is applied over the passivation film. Openings aredefined in association with the positions of the bonding pads designatedat numerals 86, 87, 88 and 89 so as to expose up to the third layeraluminum wiring. Afterwards, copper having a thickness of 1 μm isdeposited by a sputtering method and the relocation wirings 90 arepatterned on the DRAM chip as shown in FIG. 13.

Next, as shown in FIG. 14, a resin having a thickness of 3 μm is appliedonto the relocation wirings 90, and pad open holes 91 are defined onlyin areas in which solder bump electrodes are displaced, and areas forbringing probes for probe inspection into contact therewith.

Further, a Cr film having a thickness of 0.3 μm is deposited by thesputtering method and patterned to thereby form barrier layers (undermetal layers) 92 for the solver bump electrodes as shown in FIG. 15. Thebarrier layer 92 functions as a barrier layer for blocking thegeneration of an intermetallic compound by a reaction between tin (Sn)and copper (Cu) contained in each solder bump electrode. Referencenumerals 90 and 90 a respectively indicate relocation wirings exposedfrom the pad open holes 91, which in turn are used as the pads for probetesting as described above. In particular, the relocation wirings 90 aare used to supply the voltages VDD and Vbb′ for programming theantifuse 1.

Finally, as shown in FIG. 16, solder bump electrodes 93 and 93 a eachhaving a diameter of 200 μm, for example, are formed on theircorresponding barrier layers 92, and a wafer process for the flip-chiptype DRAM is completed. The solder bump electrodes 93 a are respectivelyelectrodes for forcedly bringing terminals for applying the voltages VDDand Vbb′ used to program the antifuse 1 to the source voltage Vcc andthe ground voltage Vss. Afterwards, a probe test, and relieving andselecting tests based on the breakdown of the substrate gate capacitor(antifuse) 1 are executed. Finally, the cutting of chips from the waferis carried out. The cut-out flip-chip type DRAMs are face-down bondedonto a printed circuit board and the injection and curing of a fillerare effected thereon, whereby products are brought to completion. Whenthe product is implemented on the substrate, the pairs of solder bumpelectrodes 93 a are connected to their corresponding power wirings forthe source voltage Vcc and the ground voltage Vss.

A vertical cross-section of a principal portion of the antifuse circuit85 employed in the flip-chip type DRAM is shown in FIG. 17. A deepn-type well region 11 is formed on a p-type silicon substrate 10, and ashallow p-type well region 13 is formed inside the deep n-type wellregion 11. A shallow p-type well region 12 is formed next to the deepn-type well region 11. A selection transistor 2 separated by elementisolating regions 14 and comprising n-type low-concentrationsource/drain regions 95, an n-type drain region 18, an n-type sourceregion 19, a gate oxide film 15 and a gate electrode 17 employed in acell transistor of a DRAM memory cell is provided in a surface region ofthe shallow p-type well region 12. An antifuse 1 separated by elementisolating regions 4 and comprised of a gate capacitance oxide film 16, agate capacitance electrode 17 and a p-type substrate connecting diffusedlayer 20 is provided in a surface region of the shallow p-type wellregion 13. The gate capacitance electrode 17 is connected to the n-typesource region 19 of the selection transistor 2. Owing to the provisionof the n-type low-concentration source/drain regions 95 in the selectiontransistor 2, a source/drain withstand voltage can be improved from 7Vto 10V, thereby making it possible to improve the reliability of thetransistor.

<<Flip-chip Type System LSI>>

A function block diagram of a flip-chip type system LSI according to athird example of a semiconductor integrated circuit of the presentinvention is shown in FIG. 18. Although not restricted in particular,the system LSI 101 shown in the same drawing has a large number of pads102 such as probe testing metal pads, metal pads for taking outrelocation wirings (lead wires) to bump electrodes, etc. all of whichare disposed at the peripheral edge of a semiconductor substrate 100. Anexternal input/output circuit 103 and an analog input/output circuit 104are provided inside an area for the pads 102. The external input/outputcircuit 103 and the analog input/output circuit 104 use an externalpower supply relatively high in level, like 3.3V as an operating powersupply. A level shifter 105 reduces the external power supply to aninternal source voltage like 1.8V. A dynamic random access memory (DRAM)106, a central processing unit (CPU) 107, a cache memory (CACH) 108, alogic circuit (LOG) 109, a phased-locked loop (PLL) 110, ananalog-digital converter (ADC) 111, and a digital-analog converter (DAC)112 are provided inside the level shifter 105. Reference numerals 113respectively indicate antifuse circuits, which are used to relieve thedefect or malfunction of the DRAM 106. The DRAM 106, CPU 107, LOG 109and CACH 108 are activated with the internal source voltage like 1.8Vsupplied from the level shifter 105 as an operating power supply.However, the DRAM 106 boosts the internal source voltage to form a wordline selecting level and uses the boosted voltage as an operating powersupply for a word driver or the like.

In FIG. 18, designated at numerals 114 and 115 are respectively powerpads dedicated for the antifuse circuits 113. The power pad 114 is apower pad to which a breakdown voltage VDD (=5V) is applied uponbreakdown of the antifuse 1 and to which a source voltage Vcc (=3.3V) isapplied upon the normal operation. The other power pad 115 is suppliedwith a substrate voltage Vbb′ (=−5V) upon breakdown of the antifuse(substrate gate capacitor) 1 and is fixed to a ground potential Vss(=0V) upon the normal operation.

A vertical section of a device structure for the antifuse circuits,logic circuit and external input/output circuit shown in FIG. 18 isillustrated in FIG. 19 by way of example.

A deep n-type well region 121 having a depth of 2 μm, a shallow n-typewell region 124 having a depth of 1 μm, and shallow p-type well regions122 and 123 each having a depth of 0.8 μm are disposed on a p-typesilicon substrate 120 having a resistivity of 10 Ω cm. A substrate gatecapacitor (antifuse) 1 is placed within the shallow p-type well region123 and is comprised of a thin gate oxide film 127 having a thickness of4 nm, a p-type substrate connecting diffused layer 130, and a gateelectrode 128 which is comprised of an n-type polysilicon film having athickness of 0.2 μm and has a gate length of 0.3 μm. Within the shallown-type well region 124, a selection transistor 2 is separated by elementisolating regions 125 having a thickness of 0.3 μm and is formed of ap-type drain region 135, a p-type source region 134, a gate oxide film126 having a thickness of 8 nm, and a gate electrode 129, which iscomprised of a p-type polysilicon film having a thickness of 0.2 μm andhas a gate length of 1 μm. The gate electrode 128 of the substrate gatecapacitor 1 and the p-type source region 134 of the selection transistor2 are connected to each other by contact plugs 142 with tungsten (W)embedded therein and first layer metal wirings 143.

Within the shallow p-type well region 122, an n channel transistor 4operated at a source voltage of 1.8V is separated by its correspondingelement isolating regions 125 and formed of an n-type drain region 137,an n-type source region 136, a thin gate oxide film 127 having athickness of 4 nm, and a gate electrode 130 which is comprised of ann-type polysilicon film having a thickness of 0.2 μm and has a gatelength of 0.2 μm.

Also within the shallow p-type well region 122, an n channel transistor5 is separated by its corresponding element isolating regions 125 andformed of an n-type drain region 139, an n-type source region 138, athick gate oxide film 126 having a thickness of 8 nm, and a gateelectrode 131 which is comprised of an n-type polysilicon film having athickness of 0.2 μm and has a gate length of 0.4 μm.

A 100 nm-thick silicon nitride film 140 deposited by a CVD method isdisposed over the transistors 4 and 5 for the purpose of self-alignmentcontact formation. Contact plugs 142 and first metal wirings 143comprised of a 0.5 μm-thick aluminum film both of which are provided atdesired positions of a 1 μm-thick contact interlayer film 141 flattenedby a CMP method, first interlayer plugs 145 and second layer metalwirings 146 comprised of the 0.5 μm-thick aluminum film both of whichare provided at desired positions of a 1 μm-thick first interlayer film144 flattened by the CMP method, a second interlayer plug 148 and athird layer metal wiring 149 comprised of the 0.5 μm-thick aluminum filmboth of which are provided at desired positions of a 1 μm-thick secondinterlayer film 147 flattened by the CMP method, a third interlayer plug151 and a fourth layer metal wiring 152 comprised of a 1 μm-thickaluminum film both of which are provided at desired positions of a thirdinterlayer film 150 having a thickness of 0.8 μm, a fourth interlayerfilm 153 having a thickness of 0.8 μm, and a fifth layer metal wiring154 comprised of an aluminum film having a thickness of 1 μm aredisposed over the transistors 4 and 5.

In the system LSI 101, the thickness of the gate oxide film of each MIStransistor is classified into two types as described above. Circuits,each of which needs to ensure some withstand voltage (voltagewithstanding breakdown of gate oxide film) with respect to the operatingvoltage of the MIS transistor, e.g., the external input/output circuit103, analog input/output circuit 104, DRAM 106, ADC 111 and DAC 112 arenot restricted in particular but include MIS transistors each having agate length of 0.4 μm and a gate oxide film thickness of 8 nm when a 0.2μm process technology is used. On the other hand, circuits each using adeboosted relatively low internal voltage as an operating source orpower supply, i.e., the logic circuit 109, cache memory 108, and CPU 107comprise MIS transistors each having a gate length of 0.2 μm and a gateoxide film thickness of 4 nm. Although not restricted in particular, thelevel shift circuit 105 includes MIS transistors having both gate oxidefilm thicknesses. The antifuse 1 makes use of a gate oxide film of 4 nmand has been considered so as to avoid the utilization of a voltageexcessively high in level for the purpose of dielectric breakdown.

<<Relieving Circuit of DRAM>>

One example of a specific circuit configuration for relieving defectivebits of the DRAM employed in the system LSI shown in FIG. 18 will bedescribed.

One example of the DRAM 106 is shown in FIG. 20. The DRAM 106 is arelatively large-capacity readable/writable memory utilized as a workmemory or a main memory of a CPU 107. The DRAM 106 has a large capacitylike, e.g., a few GHz according to an increase in the scale of thesystem. Each of memory cell arrays 106MA of the DRAM 106 has a redundantword line WLdR in addition to normal word lines WLd_0 through WLd_Nd.Selection terminals of normal dynamic memory cells are connected totheir corresponding normal word lines WLd_0 through WLd_Nd, andselection terminals of redundant dynamic memory cells are connected tothe redundant word line WLdR. Data input/output terminals of the memorycells are connected to their corresponding bit lines BLd_0 throughBLd_Md. Although not illustrated in the drawing in particular, the bitlines BLd_0 through BLd_Md have folded bit-line structures folded backwith a sense amplifier as the center. The bit lines BLd_0 through BLd_Mdare commonly connected to a common data line 106CD through Y selectorsYSd_0 through YSd_Md.

One of the word lines WLd_0 through WLd_Nd and the redundant word lineWLdR is selected by an X decoder 106XD. One of the Y selectors YSd_0through YSd_Md is turned on by a decode output of a Y decoder 106YD. Itshould be understood that the memory cell array 106MA and the Yselectors YSd_0 through YSd_Md are provided as N sets as viewed in theobverse and reverse directions of the paper in FIG. 20. Thus, whenselecting operations are carried out by the X decoder 106XD and the Ydecoder 106YD, the input/output of data is effected on the common dataline 106CD in N-bit units. Write data is supplied a data buffer 106DBfrom a data bus DBUS. In accordance with the input data, the mainamplifier 106MA drives one bit line through the common data line 106CD.Upon a data read operation, the main amplifier 106MA amplifies read datatransferred from the corresponding bit line to the common data line106CD and outputs it from the data buffer 106DB to the data bus DBUS.

Which word line of the normal word lines WLd_0 through WLd_Nd should bereplaced with the redundant word line WLdR for the purpose of itsselection is determined by relief information stored in a relief addressstorage circuit 160. While the details thereof will be described later,the relief address storage circuit 160 has the antifuse circuits 113corresponding to the number of bits necessary to store relief addresses.

The relief information stored in the relief address storage circuit 160is supplied to an address comparator 161. When the relief informationoutputted from the relief address storage circuit 160 is effective orvalid, the relief information is compared with a row address signaloutputted from an address buffer 106AB by the address comparator 161.When they are found to coincide with each other, a detection signal HITBis brought to a logical value “0” (low level). Except when they coincidewith each other, the detection signal HITB is brought to a logical value“1” (high level). The X decoder 106XD and the Y decoder 106YD aresupplied with address signals on an address bus ABUS through the addressbuffer 106AB and decode the supplied address signals, respectively.Particularly when the detection signal HITB supplied from the addresscomparator 161 is of the logical value “1” that means inconsistency, theX decoder 106XD decodes the row address signal outputted from theaddress buffer 106AB. On the other hand, when the detection signal HITBis of the logical value “0” that means consistency, the decoding of therow address signal outputted from the address buffer 106AB is prohibitedand the X decoder 106XD selects the redundant word line WLdR as analternative to it. Thus, a memory access related to each defective wordline is replaced by a selecting operation of a redundant memory cellrelated to the redundant word line WLdR.

A timing controller 106TC performs internal timing control of the DRAM106. The timing controller 106TC is supplied with strobe signals such asa read signal and a write signal, etc. from the CPU 107 through acontrol bus CBUS and supplied with address signals corresponding toplural bits, which are regarded as memory selection signals, from theaddress bus ABUS. When the timing controller 106CT detects the operationselection of the DRAM 106, the circuits such as the X decoder 106XD,etc. are activated. When the read operation is specified by the readsignal, information stored in a memory cell selected in the memory cellarray 106MA is outputted to the data bus DBUS through the main amplifier106MA and the data buffer 106DB. When the write operation is specifiedby the write signal, data inputted via the data buffer 10DB and the mainamplifier 106MA is written into the corresponding memory cell selectedin the memory cell array 106MA.

One example of the antifuse circuit 113 corresponding to one bit, whichis employed in the relief address storage circuit 160, is shown in FIG.21. The antifuse circuit 113 has a detection unit 113A and an antifusesetting unit 113B. One capacitance electrode of an antifuse 1 like thesubstrate gate capacitor is connected t a terminal CGND connected to thepower pad 115, whereas the other capacitance electrode thereof isconnected to a node VSEN through a p channel transistor T5. −5V isapplied to the terminal CGND upon dielectric breakdown of the antifuse1, and 0V is applied thereto upon the normal operation. The gate of thetransistor T5 is connected to a ground voltage VSS and blocks thetransfer of a negative voltage applied to the terminal CGND upondielectric breakdown of the antifuse 1 to the node VSEN side.

The voltage VDD is applied to the node VSEN through a p channeltransistor T6. Further, the voltage VDD is applied thereto through aseries circuit which comprises p channel transistors T7 and T8. Thetransistor T6 is turned on according to a low level (reset instructionlevel) of a reset signal RSTB, whereas the transistor T7 is turned on bya low level (selection level) of a select signal AiB of an antifuse 1.The transistor T8 is switch-controlled in response to the feedback of adetection signal FAi of the detection unit 113A.

In the detection unit 113A, p channel transistors T4 and T3 areseries-connected to the node VSEN. The transistor T3 is connected to aterminal VDC through a pair of p channel transistors T1 and T2 connectedin parallel form. The terminal VDC is connected to the power pad 114.The gate electrode of the transistor T1 is supplied with an internalcontrol signal brought to a high level upon the access operation of theDRAM. The gate electrode of the transistor T2 is feed-back connected tothe drain of the transistor T3 through an inverter INV1.

While the transistor T4 may be an n channel transistor, its drivecapability or power (W/Lg) is set higher than that of the transistor T3and the input level of the inverter INV1 is adjusted in this condition.

When the antifuse 1 shown in FIG. 21 is brought into dielectricbreakdown, the terminal VDC is set to a breakdown voltage VDD like 5Vand the terminal CGND is set to a negative substrate bias voltage Vbb′like −5V. Upon the first operation, the reset signal RSTB is temporarilybrought to a low level and the node VSEN is initially set to the voltageVDD. The signal TRAS is rendered high in level and the signal AiB isrendered low in level, whereby the output of the inverter INV1 is firstset to a low level. In this condition, the node VSEN is supplied withthe breakdown voltage VDD through the transistors T7 and T8. Thus, apotential difference of about 10V is developed in one capacitanceelectrode of the antifuse 1, whereby the antifuse 1 undergoes theelectrical breakdown. The antifuse 1 subjected to the dielectricbreakdown changes from a high-resistance state to a low-resistancestate, so that the voltage applied to the node VSEN is reduced. Theinverter INV1 detects it and thereby cuts off the transistor T8, wherebythe state of the application of the high voltage to the antifuse 1 isautomatically stopped.

Upon the access operation of the DRAM, the terminal VDC is set to 3.3V,the terminal CGND is set to 0V, and the signals RSTB and AiB both hold ahigh level respectively, whereas the signal TRAS is set to a low level.If the antifuse 1 is already subjected to the dielectric breakdown, thenthe detection signal FAi is brought to a high level. If not so, then thedetection signal FAi is brought to a low level.

A circuit configuration for storing one relief address is illustrated inFIG. 22 as one example of an relief address storage circuit 160 usingthe antifuse circuits 113. The configuration of each antifuse circuit113 is simplified in its diagrammatic representation. For example, n+1antifuse circuits 113 are provided. Each individual antifuse circuits113 are commonly supplied with the signal TRAS and the reset signalRSTB. One capacitance electrodes of respective antifuses 1 are commonlyconnected to the terminal CGND. Further, the respective antifusecircuits 113 are individually supplied with n+1-bit program addresssignals A0B through AnB in a bit-correspondence relationship and outputn+1-bit signals FA0 through FAn in a bit-correspondence relationship.Each of the bits for the program address signals A0B through AnBcorresponds to the selection signal AiB. The program address signals A0Bthrough AnB result in level inverted signals corresponding to respectivebits for address signals A0 through An indicative of addresses (failureor defective addresses) to be relieved. Each of the program addresssignals is supplied from its corresponding external address inputterminal in a program mode of each antifuse circuit 113.

In FIG. 22, a circuit, which comprises n channel transistors T9 and T10and a p channel transistor T11, is a circuit which is capable ofexternally applying a negative voltage (e.g., −5V) to the terminal CGNDcommon to the large number of antifuse circuits 113 upon a fuse programoperation and applies a ground voltage VSS to lines connected to theterminal CGND upon the normal operation for itself. Namely, thetransistor T11 is a MIS transistor for applying a voltage VDD level fornormally bringing the transistor T9 to an on state to the gate electrodeof the transistor T9. The transistor T11 is a MIS transistor whose Lg(gate length) is large and whose internal resistance is high. When thevoltage at the terminal CGND drops to a negative voltage, the transistorT10 is turned on so that the voltage applied to the gate of thetransistor T9 is brought to a negative voltage near the negative voltageat the terminal CGND, thus turning off the transistor T9. Thus, thepower lines connected to the terminal CGND are supplied with a groundvoltage VSS according to the turning on of the transistor T9 upon thenormal operation, and the reverse flow of a current from the groundvoltage VSS to the negative voltage at the terminal CGND is preventedupon a program operation of each antifuse 1.

According to the circuits shown in FIGS. 21 and 22, the antifuse 1 ofthe antifuse circuit 113 corresponding to each low-level bit of theprogram address signals A0B through AnB is brought into dielectricbreakdown upon the program operation of the antifuse 1. Each of thesignals FA0 through FAn outputted in response to the program stateresults in the intended address signal to be relieved.

FIG. 23 is a timing chart taken when the antifuse 1 undergoes anelectrical breakdown, and FIG. 24 is a timing chart for describing theread operation of a detection signal FAi, respectively.

In FIG. 23, the dielectric breakdown of each antifuse 1 is selectedaccording to the low level of the address designation signal AiB andcarried out by applying the voltage VDD to the node VSEN and applyingthe negative voltage to the terminal CGND. Since the transistor T5 is ofa p channel MIS transistor, the level of the voltage VDD at the nodeVSEN can be applied to the upper terminal (node VSEN) of thecorresponding antifuse 1 without a level loss. Since a current pathextending from VDD to CGND via VSEN does not exist in a programnon-selected antifuse 1 in which a program address signal AiB is broughtto a high level, the antifuse 1 is not broken. When the antifuse 1 isbroken, it is brought into a low-resistance state such as a short state,and even the upper terminal of the antifuse 1 becomes negative. However,the node VSEN is not reduced to VSS (ground voltage)+Vthp (thresholdvoltage of p channel MIS transistor) or less by the transistor T5. Thetransistor T4 may be either a p channel MIS transistor or an n channelMIS transistor. However, it may preferably transfer a reduction in thelevel of the node VSEN to the input of the inverter INV1 to therebychange the detection signal FAi from low to high levels. Thus, thecurrent path extending from VDD to CGND via VSEN is not developed andother antifuses 1 not yet subjected to breakdown proceed to breakdown.While the negative voltage at the terminal CGND is applied between thegate and source of the transistor T5 and between the source thereof andan NWELL (n-type well region), the absolute-value voltage with theground voltage VSS as the reference may be small as compared with theuse of only the high voltage on the positive side. Therefore, thepn-junction of the transistor T5 is not broken.

The signal AiB is rendered high in level and the signal TRAS is renderedlow in level to thereby carry out the reading of the antifuse 1. Uponfuse reading at the time that the antifuse 1 is being broken, a currentflows into the terminal CGND (=0V) through the transistors T1, T3, T4,T5 and antifuse 1 from the voltage VDD side, so that the node VSEN isbrought to a low level and the signal FAi outputted from the inverterINV1 is brought to a high level. On the other hand, upon reading of eachantifuse 1 placed in a non-destructive state, the node VSEN does notfall below the voltage VDD, and the detection signal FAi is maintainedat a high level. The transistor T4 may be either a p channel MIStransistor or an n channel MIS transistor. However, the transistor T4 isset in such a manner that the drive capability thereof is set higherthan that of the transistor T3 and the input of the inverter INV1 canreliably be determined by the level of the node VSEN. The transistor T4is provided for the separation between the operations of the detectionunit 113A and the fuse setting unit 113B. The transistor T4 may beomitted according to a subsequent-stage circuit configuration using thedetection signal FAi.

A device section illustrative of the transistors T5, antifuses 1 andtransistor T9 shown in FIG. 22 is illustrated in FIG. 25 by way ofexample.

In FIG. 25, reference numeral 170 indicates a p-type semiconductorsubstrate (P-Sub(VSS)), reference numeral 171 indicates a deep n-typewell region (DW(VDD)), reference numerals 172 and 173 indicate shallown-type well regions (NW(VSS)), and reference numerals 174 and 175indicate shallow p-type well regions (PW), respectively.

In the structure shown in FIG. 25, the p-type well region 174 of theantifuse 1 can be reduced to a negative potential by using a triple wellstructure based on the deep n-type well region 171. The n channel MIStransistor T9 is also formed in the same p-type well region 171. Thetriple well structure is a structure wherein well voltages for n channelMIS transistors of a memory array and its peripheral circuit canrespectively independently be set to the optimum voltages and heavilyused in a DRAM to enhance noise resistance of the memory array. The nchannel MIS transistors for the normal peripheral circuit are providedin the p-type well regions 175 on the semiconductor substrate 170 andtheir well potentials are set as a ground potential VSS.

While an insulating film for the antifuse 1 is formed thin in FIG. 25, aDRAM memory cell structure similar to one described in U.S. Pat. No.5,324,681 to make it easy to break the antifuse 1. When tantalum oxide(Ta₂O₅) is used in particular, the structure is asymmetric in withstandvoltage and low in withstand voltage where a negative voltage is appliedto the terminal CGND. This is advantageous to the structure shown inFIG. 21. In the antifuse 1, a gate oxide film having a thin one of twotypes of film thicknesses can be used as a gate oxide film in a gateprocess using the two types of film thicknesses (e.g., tOX=4 nm or 8 nm)except when each memory cell is used.

One example of the address comparator 161 is shown in FIG. 26. Theaddress comparator 161 has selector units 162 which respectivelytransfer respective bits corresponding to access address signals A0through A9 in inversion or non-inversion form according to the logicalvalues of the corresponding bits of the detection signals FA0 throughFA9. The selector unit 162 to which A0 and FA0 are inputted, outputs aninverted level of the address bit A0 when the detection signal FA0 ishigh in level (when the antifuse 1 is placed in a dielectric breakdownstate) and outputs a non-inverted level of the address bit A0 when thedetection signal FA0 is low in level (when the antifuse 1 is placed in anon-dielectric breakdown state). Other selector units 162 are alsoconfigured in a manner similar to the above. The breakdown of theantifuse 1 is carried out when the corresponding program address AiB islow in level. Since each detection signal FA is high in level in thiscondition, the outputs of all the selector units 162 are brought to alow level (logical value “0”) over all the bits when the access addresssignals A0 through A9 equal to inverted signals of respective bits forprogram addresses A0B through A9B are inputted. If the inverted signalsof the respective bits for the program addresses A0B through A9B and theaccess address signals A0 through A9 differ even one bit, then theoutput of any of the selector units 162 is brought to a high level(logical value “1”). NOR and NAND gates 163 and 164 are provided todetect such a condition. A relief enable signal FEB is also supplied toone NOR gate 163. The relief enable signal FEB is a signal brought to alow level where the relieving of each defective bit is done. Such oneantifuse circuit as shown in FIG. 21 by way of example is assigned asits signal source. When each access address coincides with a defectiveaddress, a detection signal HITB outputted from the NAND gate 164 isrendered low in level, whereas the detection signal HITB is brought to ahigh level when they do not coincide with each other. A program for theantifuse 1, which is used for relieving, is done as one sphere of a testprocess by setting a program mode to the system LSI. The setting of theprogram mode can be carried out through a mode terminal, for example.

While the description of FIG. 20 has been made with the word-line reliefas one example, the relieving of bits or the relieving of the two may beperformed. While a description has been made of the case in which theantifuse set for programming the defective address is provided as oneset, it is needless to say that the provision of a plurality of antifusesets can cope with a plurality of faulty or defective addresses.

<<Setting of Mode by Antifuse>>

A configuration, which allows mode setting in place of a bonding option,will be described as an example in which the antifuse circuit is usedfor function setting.

As an example of the bonding option, a description will first be made ofthe selection of both the number of banks and the number of parallelinput/output bits for data in such a DRAM as shown in FIG. 12. In anexplanatory view of a bonding option shown in FIG. 27, the operationmodes of the DRAM are determined according to whether three option padsBOPIN0B, BOPIN1B and BOPIN2B are brought to floating or connected to aground voltage VSS. The state of the option pad BOPIN0B is brought to atwo-bank enable signal BANK2B via an input protection circuit and afirs-stage input circuit 170. The signal BANK2B means two banks (2Bank)according to a high level, whereas it means four banks (4Bank) accordingto a low level. The input protection circuit and first-stage inputcircuit 170 are given as illustrated in FIG. 28 by way of example. If aninput BOPINiB is low in level (ground voltage), then an output BOiB isalso brought to a low level. If the input BOPINiB is placed underfloating, then the output BOiB is brought to a high level.

The states of the option pads BOPIN1B and BOPIN2B are supplied to abonding option determination circuit 173 through the input protectioncircuit and first-stage input circuit 171 and 172, where the states ofsignals BPX4, BPX8 and BPX16 each indicative of the number of parallelinput/output bits for data are determined according to the states of theinputs. The input protection circuit and first-stage input circuit 171and 172 have logical paths illustrated in FIG. 28 by way of example. Thebonding option determination circuit 173 has a logical configurationshown in FIG. 29. According to this logic, when an input BO1B is high inlevel, a signal BPX8 is brought to a high level regardless of an inputBO2B, whereas if the input BO1B is low in level, then signals BPX8 andBPX16 are respectively brought to a high level regardless of the inputBO1B.

If the operation modes settable by the bonding option are put in order,then they are represented as shown in FIG. 30. Thus, according to thestates of the three option pads in the DRAM, six cases, i.e.,combinations of the number of banks 2 or 4 and the number of parallelinput/output bits four, eight or sixteen bits can be selected. Thisbonding option is executed in a bonding process step in an assemblyprocess subsequent to the completion of a wafer process. The internalsignals BANK2B, BPX4, BPX8 and BPX16 obtained in this way are set tounillustrated subsequent-stage circuits and used for control on anaddress buffer and a predecoder, control on a main amplifier, control onan output buffer, etc.

A configuration which allows a function selection equivalent to thebonding option through the use of each antifuse circuit, is shown inFIG. 31 by way example. Since no bonding step is set upon chip assemblyin the flip-chip type semiconductor integrated circuit, the functionselection cannot be performed in the case of the above bonding optionsystem. The conventionally available laser fuse cannot be used either.The configuration of FIG. 31 is one in which these points have beentaken into consideration. This is one wherein antifuse circuits AF0through AF2 are applied and the selection of functions can electricallybe performed according to the setting of programs to the antifusecircuits AF0 through AF2 even after a wafer process has been completedand bump electrodes have been formed. Such an antifuse circuit as shownin FIG. 21 by way of example can be used for the antifuse circuits AF0through AF2 shown in FIG. 31. The programs for the antifuse circuits AF0through AF2 are executed in test modes. Namely, each antifuse circuitfirst enters an antifuse setting mode. By using a WCBR (for enabling awrite enable signal WE and a column-address-strobe signal CAS prior to arow-address-strobe signal RAS being enabled) test mode and part ofaddress signals in a DRAM, for example, each antifuse circuit may enterthe operation mode as one of the test modes. A breakdown voltage VDD isapplied to the terminal VDC and a negative voltage Vbb′ is applied tothe terminal CGND. A program address for designating each fuse to besubjected to dielectric breakdown is supplied from its correspondingexternal address input terminal as a normal address signal. Theoperation modes settable by the antifuses AF0 through AF2 arerepresented as shown in FIG. 32, and settable functions correspond toFIG. 30.

Incidentally, the function selection described herein was an exampleillustrative of the configuration of the number of the parallel datainput/output bits in the DRAM and the selection of the number of banks.While the switching between operation modes such as a first page, an EDOmode (Extended Data Out Page Mode), a static column, etc. has beencarried out by use of bonding options even in the case of a standardDRAM in addition to the above, the switching between these can alsoeasily be performed by antifuse programming in the same manner asdescribed above.

<<Trimming by Antifuse>>

A description will next be made of a case in which each antifuse is usedfor trimming correction of each internal voltage. When a voltage VPERIis generated within a chip for a DRAM, the level thereof changes underthe influence of process variations. The voltage VPERI is measuredaccording to a probe test. If it falls outside an allowable range, thena trimming circuit for correcting it is utilized. The antifuse circuitcan be used for its trimming setting.

One example of a trimming setting circuit is shown in FIG. 33. Thetrimming setting circuit has three antifuse circuits AF10 through AF12.Signals outputted from the respective circuits are supplied to atrimming decoder 180 as 3-bit complementary signals FT1, FTB1 throughFT3 and FTB3. The antifuse circuit shown in FIG. 21 or the like can beused for the antifuse circuits AF10 through AF12. AiB through AkB means3-bit program address signals respectively. The trimming decoder 180decodes the 3-bit complementary signals and brings one of eightselection signals TRM0 through RTM7 to a selected level. The logic ofthe decoder 180 is shown in FIG. 34 as an example. The selection signalsTRM0 through TRM7 are set as selected signals corresponding to dividedvoltages of a resistance type voltage divider 183. Namely, a referencevoltage generated by a reference voltage generator 181 is by-resistancedivided by a series circuit comprised of a plurality of resistors R1.The divided voltages are selected by their corresponding n channelselection MIS transistors M1 through M7. The selection signals TRM0through TRM7 are set as gate control signals for the selection MIStransistors M0 through M7. Each of the voltages selected by theselection MIS transistors M0 through M7 is supplied to its correspondinginversion input terminal of an op amplifier 182 as a reference voltageVREF. The output of the op amplifier 182 is connected to a gateelectrode of a p channel output transistor M8 connected to a powerterminal Vcc. A potential applied to the drain of the output transistorM8 is set as a voltage VPERI and a voltage obtained by dividing thevoltage VPERI is set as a voltage fed back to a non-inversion inputterminal of the op amplifier 182. The voltage VPERI produces levelscorresponding to twice to a few times the reference voltage VREFaccording to the by-resistance divided state of the fed-back voltage.When the MIS transistor located on the upper side of FIG. 33, of theselection MIS transistors M1 through M7, is turned on, a relativelyhigh-level reference voltage VREF is obtained. When the MIS transistorlocated on the lower side thereof is turned on in reverse, a relativelylow-level reference voltage VREF is obtained. In a state in which thefuses of the antifuse circuits AF10 through AF11 are not programmed atall, a central level is normally obtained through the use of theselection MIS transistor M4.

The trimming circuit for such a voltage regulator as described above canbe applied even to circuits such as an ADC, etc. The trimming circuit isnot limited to the voltage regulator and can be applied even to acircuit or the like for correcting a delay time, which makes use ofresistive and capacitive elements.

<<Testing Pads of Flip-chip Type Semiconductor Integrated Circuit>>

A description will next be made of testing pads of a flip-chip typesemiconductor integrated circuit. Here, a flip-chip type means the formof a mounting technology of placing an element forming surface (circuitforming surface) of a semiconductor chip in an opposing relationship toa printed circuit board to be mounted, and connecting electrodes formedon the element forming surface and electrodes on the printed circuitboard to one another.

A plan view of a flip-chip type DRAM mentioned as one example herein isfirst shown in FIG. 35. As shown in the same drawing, a large number oftesting pads 209 are arranged in a central portion of a chip for aflip-chip type DRAM 210 along the longitudinal direction thereof.Further, a large number of bump electrodes 208 are laid out outside thetesting pads 209 in area array form.

FIG. 36 is a plan view showing the manner in which part of FIG. 35 isshown in enlarged form and a surface insulating layer is removed toallow routing of relocated wirings to be brought into view. Namely, FIG.36 shows the state of connections of testing pads and bump electrodes.The testing pads 209 are roughly divided into pads 209 a connected totheir corresponding bump electrodes 208 through relocation wirings 205,and pads 209 b disconnected from the bump electrodes. One testing pads209 a are connected to their corresponding power-supply or signalinput/output bonding pads (202 a) of bonding pads (202) not shown inFIG. 36. Further, the relocation wirings 205 are drawn out of thecorresponding bonding pads (202 a) and connected to their correspondingbump electrodes 208. The other testing pads 209 b are not used in thefinal use stage of the flip-chip type DRAM 210 and connected tounillustrated bonding pads (202 b) used in a probe testing stage or thelike. The corresponding bonding pads (202 b) are disconnected from thebump electrodes 208.

FIGS. 37 through 43 are respectively cross-sectional views showing amethod of manufacturing the flip-chip type DRAM shown in FIG. 35. Asection structure along the relocation wirings 205 extending from thepower-supply or signal input/output bonding pads 202 a to the bumpelectrodes 208, and a section structure of the bonding pad 202 b portiondedicated for probe testing are shown while following respectivemanufacturing stages.

FIG. 37 shows a wafer section in a state in which bonding pads 202 (202a and 202 b) are formed on the surface of a DRAM chip 201 having a largenumber of circuit elements formed on a semiconductor substrate and arecovered with a protective layer 203 except for openings for the bondingpads 202. One shown herein is placed in a stage of the completion of theconventional wire-bonding connecting wafer.

A lower insulating layer 204 is first formed on the surface of the waferas shown in FIG. 38. Portions of the bonding pads 202 (202 a and 202 b)are made open or exposed at the lower insulating layer 204.

Next, as shown in FIG. 39, a relocation wiring 205 is formed up to theposition to form each bump electrode from the bonding pad 202 a and atthe same time a relocation wiring layer 295 is formed with respect tothe pad 202 b dedicated for testing.

As shown in FIG. 40, a surface insulting layer 206 is formed, andimmediate upper portions of the bonding pads 202 (202 a and 202 b) ofthe relocation wiring layers 205 and 295 and a portion for forming eachbump electrode are exposed.

Further, as shown in FIG. 41, an under bump metal or metallurgy 207 isformed in the bump electrode forming portion, and under bump metallurgylayers 297 are simultaneously formed over the bonding pads 202 (202 aand 202 b).

The under bump metallurgy layers 297 just or directly over the bondingpads 202 (202 a and 202 b) formed in the above-described manner resultin a testing pad 209 a corresponding to each power or signalinput/output bonding pad 202 a, and a testing pad 209 b corresponding toeach test-dedicated bonding pad 202 b.

Next, as shown in FIG. 42, the leading ends of probes 211 are broughtinto contact with their corresponding testing pads 209 a and 209 b toperform a probe test, whereby the relief of each defective product byuse of the redundancy of a circuit, the selection of functions, thesorting of non-defective products and defective products, etc. areexecuted.

Next, as shown in FIG. 43, a bump electrode 208 is formed on the underbump metallurgy 207 by solder, and the completed wafer is cut so as tobe separated into each individual chips (dicing), thereby obtainingflip-chip type DRAMs.

While aluminum or an aluminum alloy is used as a material for thebonding pad 202 or its surface, copper or another metal may be usedaccording to the type of a wiring material used inside a semiconductorelemental device.

In addition to inorganic films such as a silicon oxide film, a siliconnitride film, etc., an organic film like polyimide, and a combination ofthese are used as the material for the protective layer 203.

The material for the lower insulating layer 204 may preferably useorganic materials or substances having low elastic modulus (low modulusof elasticity) and low permittivity, like polyimide, a fluorocarbonresin, various elastomer materials to relax a stress (state ofstress/distortion) which acts on the bump electrode 208 due to thedifference in thermal expansion between a semiconductor device and aprinted circuit board after the implementation of the substrate, andreduce the capacitance of the relocation wiring 205. Here, as theelastomer materials, may be mentioned, for example, silicon and acrylicrubber materials, a polymeric material having low elastic modulus, whichhas blended these rubber materials.

The lower insulating layer 204 is formed by spin coating using varnish,printing or film bonding. The thickness of the lower insulating layer204 may preferably be about 3 μm or more from the viewpoint of thestress and the reduction in capacitance. However, when the organic filmis used for the protective layer 203, the lower insulating layer 204 ismade thinner than it or may be omitted.

A three-layer wiring structure wherein a chromium, titanium, nickel, anickel alloy or the like having a thickness of from about 0.1 μm toabout 0.5 μm is stacked or layered on the upper and lower surfaces ofcopper or a copper alloy having a thickness of about 1 μm to about 5 μm,for example, is used for the relocation wiring 205. Further, aluminumand its alloy may be used therefor.

Organic materials having low elastic modulus, like polyimide, an epoxyresin, a fluorocarbon resin, and various elastomer materials maypreferably be used as the material for the surface insulating layer 206to relax the stress which acts on the bump electrode 208.

A flexible one may be used as the insulating film (further insulatingfilm) below the relocation wiring to absorb the stress that acts on thebump electrode. The upper insulating film 206 may select a materialrelatively harder than the lower insulating film 204 from the viewpointof its protection. Described specifically, the upper insulating film 206and the lower insulating film 204 are respectively formed of aphotosensitive polyimide resin film. The amount of a solvent, molecularweight, the content of a filler, etc. prior to heat treatment (cure) arechanged to thereby make it possible to change the final hardness(elastic modulus) of the film thereof. Further, the upper and lowerinsulating films may be formed of materials different from each other.In this case, the upper insulating film 206 and the lower insulatingfilm 204 are considered to be formed of, for example, an epoxy resin anda polyimide resin respectively.

As the under bump metallurgy 207, a metal having a high solder barrierproperty, such as chromium, nickel, nickel/tungsten, nickel/copper orthe like may preferably be formed with a thickness of about 0.3 μm toabout 3 μm. Further, a golden thin-film layer having a thickness ofabout 0.1 μm may preferably be formed on the surface thereof to ensurewettability of solder and electrical connectability to each probe.

The solder bump electrode 208 can be formed by printing solder paste onthe under solder bump metallurgy 207 or transferring a solder ballmolded to a predetermined size in advance and thereafter effectingreflow on it.

The testing pads 209 are provided just or directly over both of thepower-supply or signal input/output bonding pad 202 a and the bondingpad 202 b for probe testing, thereby making it possible to execute theprobe test after the relocation wiring process. It is therefore possibleto prevent degradation in connection reliability due to damage of eachbonding pad 202 prior to the relocation wiring process.

Since an inspection is done without applying the probe 211 to thealready-formed solder bump electrode 208, the solder bump electrode 208can be prevented from deforming. It is also possible to prevent damageof the probe 211 due to the application of the probe decentered to acurved surface of the solder bump electrode 208 to the solder bumpelectrode 208.

Further, since it is not necessary to apply the probe 211 to the undersolder bump metallurgy 207 antecedent to the formation of the solderbump electrode 208, there is no fear that the layer for enhancing solderwettability, such as gold or the like formed on the surface of the undersolder bump metallurgy 207, and the solder barrier metal layer placedbelow the layer are endamaged, thus making it possible to preventdegradation in connection reliability to solder.

Further, according to the present example, since the testing pads 209are arranged in a row as shown in FIG. 36, an inexpensive cantilevertype probe can be used as the probe 211 as shown in FIG. 42. Further,since the bonding pads 202 on the normal wire-bonding wafer with norelocation wirings applied thereto, and the testing pads 209 describedherein are identical to one another in position within a chip plane, thenormal wire-bonding wafer and the probe 211 can also be sharedtherebetween.

Since the testing pads 209 enter into projected areas of the bondingpads 202 in the aforementioned flip-chip type DRAM, an increase incapacitance due to the addition of the testing pads 209 is next tonothing.

<<Function Selection Using Testing Pads>>

An example of a breakdown of the number of bonding pads employed in a 64Mbit synchronous DRAM chip and the number of external terminals employedin a conventional TSOP (Thin Small Out-line Package corresponding to akind of surface-mounted package) equipped with the chip is shown in FIG.44. Leads corresponding to the external terminals of the TSOP typepackage and the bonding pads of the chip are respectively connected toone another by wire bonding using golden thin lines.

Signal input/output bonding pads are all connected to theircorresponding external terminals of the package in one-to-onerelationship. The number of power bonding pads is greater than theexternal terminals of the package. A plurality of power bonding pads arecommonly wire-bonded to the same external terminals.

Function-selecting bonding pads are individually connected to a sourcevoltage upon wire bonding or disconnected therefrom to thereby operatethe same chips in different systems. They select the number ofinput/output bits (4 bits, 8 bits or 16 bits), the number of banks (2banks or 4 banks), etc.

Bonding pads dedicated for probe testing are used only upon probetesting and ones for observing internal operating conditions of thesynchronous DRAM chip. They are not connected to the external terminalsof the package.

Electrically unnecessary external terminals are provided in the packageexternal terminals to set an outer shape in common with anothersemiconductor device, for example. They are not connected to the bondingpads of the chip.

When relocation wirings are given to the chip like the synchronous DRAMhaving the terminal configuration of FIG. 44 to form it as a flip chip,the number of solder bump electrodes increases when the solder bumpelectrodes are provided in the completed flip-chip's product inassociation with all the bonding pads. Therefore, if these many bumpelectrodes are laid out within a limited chip area, then the intervalbetween the adjacent bump electrodes becomes narrow, the positioning atsubstrate mounting becomes difficult, and an expensive substrate isrequired.

The provision of only the testing pads 202 b with respect to somebonding pads 202 b without providing the bump electrodes as described inFIG. 36 makes it possible to execute the probe test after the relocationwiring process without an increase in the number of solder bumps.

In the case of the flip-chip type semiconductor integrated circuitprovided with the relocation wirings 205, the connections of thefunction-selecting bonding pads can be performed by any of the followingthree methods.

The first is a method of providing the solder bump electrodes 208corresponding to all the function-selecting bonding pads and selectingeach function according to wire connections on the side of the substrateon which the flip-chip type semiconductor integrated circuit is mounted.This method has an advantage in that since the same semiconductorintegrated circuit can be shared between respective specifications, thenumber of types is reduced, the management on the semiconductor makerside becomes easy, and a user is capable of selecting functions.However, the number of the bump electrodes increases and the intervalbetween the adjacent bumps incurs narrowing. Further, a user who needsto have a peculiar function alone is also requested to add substratewirings.

The second is a method for changing connected patterns of the relocationwirings 205 every individual functions. The method needs to prepare thepatterns for the relocation wirings 205 by the number of types forfunction selection. This method has a problem in that since eachfunction is fixed in a wafer wiring stage, it is hard to flexibly copewith a change in inter-type demand.

The third is a method using an electrical fuse like the antifuse 1.According to this method, all the types for function selection can beformed by the same relocation wiring patterns, and the number of solderbump electrodes does not increase. The function selection, i.e., thesetting of each antifuse 1 is carried out by applying a probe to a wafersubsequent to the formation of the under bump electrode metallurgy 207in a manner similar to the probe test. Terminals used for setting theantifuse 1 may share the use of the signal input/output and powerbonding pads 202 a connected to the solder bump electrodes 208.Alternatively, they may be provided as dedicated pads like testing padsdisconnected from the solder bump electrodes 208. The latter needs sucha circuit as being comprised of the transistors T9 through T11 shown inFIG. 22. Namely, according to the example shown in FIG. 22, the negativevoltage Vbb′ must be supplied to the terminal CGND upon programming ofeach antifuse. However, the terminal CGND can be kept floating after itsprogramming has been completed, and the terminal CGND is automaticallysupplied with the ground voltage Vss without being connected to theground voltage Vss.

Since the function selection can also be performed simultaneously withthe conventional probe test when it is carried out by each antifuse,bonding pads dedicated for antifuse setting can be regarded as the broadbonding pads 202 b dedicated for probe testing. Further, pads forapplying a probe thereto upon antifuse setting can be regarded as thebroad testing pads 209 a and 209 b.

Only the testing pads 202 b are provided for some bonding pads 202 bwithout providing the bump electrodes and used for function selection asdescribed in FIG. 36. Consequently, the function selection can becarried out after the relocation wiring process without increasing thenumber of solder bumps.

<<Relocation Wiring and Another Structure of Testing Pad>>

Another structure of a relocation wiring portion is shown in FIG. 45 inthe form of a cross-sectional view. In the structure shown in FIG. 43,the under solder bump metallurgy 207 is formed after the opening of thesurface insulating layer 206, whereas in the structure shown in FIG. 45,an under solder bump metallurgy 207 is formed on a relocation wiring 205in advance and thereafter a surface insulating layer 206 is formedthereon, and a portion directly above each bonding pad 202 and a portionfor forming a solder bump electrode 208 are made open or exposed.

Even in the case of this structure, an effect similar to the structureshown in FIG. 43 can be obtained. Since the mask necessary to form thecontour of the under solder bump metallurgy 207 by etching processing inthe structure shown in FIG. 43 becomes unnecessary for the structureshown in FIG. 45, the processing cost can be reduced. However, both thelower insulating layer 204 and the surface insulating layer 206 existdirectly below the outer peripheral portion of the solder bump electrode208 at the base thereof in the structure shown in FIG. 43, whereas onlythe lower insulating layer 204 is provided in FIG. 45. Therefore, thestructure shown in FIG. 43 is excellent in terms of the effect ofrelaxing the stress that acts on the bump electrode 208 due to, forexample, the difference in thermal expansion between the semiconductordevice and the printed circuit board after the substrate mounting.Further, the reliability of connections of the solder bump electrodeswith respect to the repetition of a change in temperature, therepetition of substrate deformation due to an external force, etc. isenhanced.

Another example of a layout configuration of testing pads is shown inFIG. 46, and its sectional structure is shown in FIG. 47 as an example.Testing pads 209 a are formed by an under bump metallurgy layer 297 on asurface insulating layer 206 on the side opposite to each solder bumpelectrode 208 with bonding pads 202 a interposed therebetween.

Even with respect to bonding pads 202 b dedicated for probe testing,testing pads 209 b are formed by the under bump metallurgy layer 297 atits adjoining portion on the surface insulating layer 206.

Since the testing pads 209 a are respectively shifted from just abovethe bonding pads 202 a and are formed of the under bump metallurgy 297,the bonding pads 202 a and relocation wirings 205 are not exposed evenif the testing pads 209 a are endamaged upon probe testing. Thus, thereis no fear that the electrical connections between the bonding pads 202a and the under bump metallurgy 207 would be cut due to corrosion or thelike developed by moisture. As compared with the structures shown inFIGS. 43 and 45 provided with the testing pads 209 at the portionsdirectly above the boding pads 202, the flat testing pads 209 can beobtained.

In the flip-chip type semiconductor integrated circuit having thestructure wherein the bonding pads 202 are arranged on the center lineof the chip or in the neighborhood thereof, and the solder bumpelectrodes 208 are disposed on both sides of their row as shown in FIG.46, the relocation wirings 205 are respectively drawn on the oppositesides alternately or at intervals of several pads on both sides of thebonding pad row. Therefore, the placement of the testing pads 209 onboth sides of the bonding pad row in divided form makes it possible toprovide testing pads 209 larger in size than those provided just abovethe bonding pad row or on the same side thereof.

Since the testing pads 209 are formed on the laminated lower insulatinglayer 204 and surface insulating layer 206, the distance extending fromeach lower semiconductor circuit element can be increased, and anincrease in capacitance due to the addition of the testing pads 209 canbe reduced.

Further, if an organic insulating film such as polyimide is used foreither one of the lower insulating layer 204 and the surface insulatinglayer 206, then the effect of reducing capacitance becomes great sinceit is lower than the normal inorganic insulating film in specificinductive capacity. If it is used for both, then the maximum effect canbe obtained.

When the organic insulating film such as polyimide or the like is usedfor the surface insulating layer 204 used as a bed for each testing pad209, it is low in elastic modulus as compared with the normal inorganicinsulating film. Therefore, even when the testing pads 209 are formed ofa hard under solder bump metallurgy 207 such as chromium, nickel, thesurfaces of the testing pads 209 are easy to deform. Therefore, the areabrought into contact with the tip of each probe 211 increases and anelectrical connectability is improved. This effect is more pronouncedlydeveloped by using the organic insulating film for both the lowerinsulating layer 204 and the surface insulating layer 206.

A further example of a section structure of a testing pad is shown inFIG. 48. FIG. 48 is different from FIG. 47 in that a mask for forming anunder bump metallurgy 207 is omitted in a manner similar to therelationship of FIG. 45 relative to FIG. 43 to thereby allow a reductionin cost. Namely, there is a possibility that since the relocation wiringlayer 205 exists in contact with the underlying portion of the undersolder bump metallurgy layer 297 on the surface of the testing pad 209 ain FIG. 47, the relocation wiring layer 205 will be exposed uponendamaging of the under solder bump metallurgy layer 297. Thus, even ifcorrosion or the like is developed in the relocation wiring layer 205 ateach testing pad 209 a portion by the placement of the testing pads 209a and solder bump electrodes 208 on the sides of the bonding pads 202 a,which are opposite to one another, it does not influence the electricalconnections between the bonding pads 202 a and the solder bumpelectrodes 208, whereby high connection reliability can be obtained.

Since each testing pad 209 a is formed on a lower insulating layer 204in the structure shown in FIG. 48, the effect of reducing capacitance islow as compared with the embodiment shown in FIG. 47. However, it can bemanufactured at low cost as compared with FIG. 47. Forming the lowerinsulating layer 204 by an organic insulating film yields the effect ofreducing an increase in capacitance due to the addition of each testingpad 209 as compared with the technology described in Unexamined PatentPublication No. Hei 8(1996)-29451 wherein the testing pads are formed onthe inorganic insulating film. Even in the case of the structure shownin FIG. 48, since the surface of each testing pad 209 formed over thelower insulating layer 204 is apt to deform by the formation of thelower insulating layer 204 with the organic insulating film,contactability with each probe 211 is improved.

A further example of a layout configuration of testing pads is shown inFIG. 49, and its sectional structure is shown in FIG. 50 as an example.Testing pads 290 a corresponding to power or signal input/output bondingpads 202 a are formed on a surface insulating layer 206 at positionswhich branch off from the course or midstream of relocation wirings 205for respectively connecting the bonding pads 202 a and an under solderbump metallurgy 207. In regard to bonding pads 202 b dedicated for probetesting, testing pads 209 b are provided at portions just above theircorresponding pads 202 b. Even if the testing pads 209 a are provided atsuch positions, the flat testing pads can be obtained as compared withthe case where they are provided at the portions just above the bondingpads 202 a. The effect of reducing capacitance is similar to FIG. 47.

The testing pads 209 a are formed so as to branch off from therelocation wirings 205. Therefore, even if the testing pads 209 a areendamaged upon probe testing, it does not influence the reliability ofelectrical connections between the bonding pads 202 a and the undersolder bump metallurgy 207.

Since the bonding pad 202 b dedicated for probe testing is regardless ofa solder bump electrode 208 in terms of the reliability of connection tothe solder bump electrode 208, it is not necessary to take intoconsideration the influence of damage of the testing pad 209 b inparticular. No problem arises even when the testing pad is provided at aportion just above the bonding pad 202 b or at an arbitrary position. Animprovement in contactability between each testing pad 202 and a probe211 by use of an organic insulating film for the surface insulatinglayer 206 or both the surface insulating layer 206 and a lowerinsulating film 204 is similar to the structure shown in FIG. 47.

FIG. 51 shows an example in which testing pads 209 b are provided onlyfor bonding pads 202 b dedicated for probe testing. The testing pads 209b respectively formed so as to be greater than the bonding pads 202 bare provided for the bonding pads 202 b dedicated for probe testing. Asto power and signal input/output bonding pads 202 a, an under solderbump metallurgy 207 antecedent to the formation of each solder bumpelectrode 208 is used to perform a probe test.

The provision of the testing pads 209 b only for the bonding pads 202 bdedicated for probe testing, to which the testing pads 209 b areessential and which is out of relation to an electrical characteristic,allows the prevention of an increase in capacitance of another bondingpad, particularly, each signal input/output wiring. Further, since thenumber of testing pads may be low and the influence on the electricalcharacteristic is not produced either, the size of each testing pad 209b and the interval between the testing pads 209 b can sufficiently beincreased.

FIG. 52 is a cross-sectional view showing an example in which each oftesting pads 209 is caused to extend from a relocation wiring 205located on the lateral side of a bonding pad 202 to a portion just abovethe bonding pad 202. Through the use of the portion just above eachbonding pad 202, the corresponding testing pad 209 flat and large insize can be formed without an increase in capacitance. Further, thedamage of the testing pad 209 does not influence the reliability ofelectrical connections. Even in the case of this structure, theformation of a surface insulating layer 206 by an organic insulatingfilm allows an improvement in contactability between the testing pad 202and its corresponding probe 211.

<<Method of Manufacturing Flip-chip Type Semiconductor IntegratedCircuit>>

Processes for manufacturing a flip-chip type semiconductor integratedcircuit are shown in FIGS. 53 through 57 every stages in the form ofperspective views.

FIG. 53 shows a completed stage of a conventional wire bondingconnecting wafer. Namely, FIG. 53 is a view showing the whole span of awafer 220 placed in the state shown in FIG. 37. The bonding pads 202 arerespectively formed in respective chips 210.

In order to manufacture the flip-chip type semiconductor integratedcircuit, lower insulating layers 204, relocation wirings 205, surfaceinsulating layers 206 and under bump metals or metallurgies 207, etc.are formed on the wafer 220 shown in FIG. 54 as illustrated in FIGS. 38through 41 by way of example. Thus, such a wafer 220 as shown in FIG. 54placed in a state in which the under bump metallurgies 207 are formed,is obtained. The state of FIG. 54 is equivalent to the state of FIG. 41as viewed in the form of a cross-section.

Next, probe tests are carried out through the use of a probe card 221wherein a plurality of probes 211 are positioned and fixed so that theirleading ends or tips are simultaneously brought into contact with aplurality of testing pads 209 (unillustrated in FIG. 55) on the wafer220 as shown in FIG. 55.

The plurality of probes 211 are simultaneously brought into contact withthe plurality of testing pads 209 to thereby simultaneously test orinspect the testing pads 209 corresponding to one chip 210 or pluralchips 210 and inspect them while their contact positions are beingshifted successively, whereby the probe tests are carried out on all thechips 210 on the wafer 220. At this time, the selection of functions andthe relief of defects can be performed simultaneously or successively byusing the same or similar another probe card 221.

A process for forming solder bump electrodes will next be explained byreference to FIG. 56 with a solder paste printing system as an example.A solder printing mask 222 in which openings 223 are defined inassociation with the layouts of under bump metallurgies 207 on thesurface of a wafer 220 as shown in the drawing, is superimposed on thewafer 220 in alignment with it, and solder paste 225 is printed thereonby a squeegee 224. In a state placed immediately after the printing, thesolder paste 225 is evenly printed on an area slightly wider than theunder bump metallurgies 207 as shown by a cross-sectional view in thedrawing. When this wafer is reflow-heated to melt the solder paste 225,solder is aggregated spherically to form solder bump electrodes 208.

The wafer 220 subsequent to the formation of the bump electrodes 208 iscut and separated into pieces of chips 210 by a dicing blade 226 asshown in FIG. 57, whereby completed products each corresponding to theflip-chip type semiconductor integrated circuit can be obtained. Thecompleted products are further subjected to a burn-in inspection andvarious final inspections for their performance, external appearance,etc. as needed. After they are subjected to predetermined markings andpackaged, they are shipmented.

<<Manufacturing Processes Subsequent to Relocation Wiring FormingProcess>>

FIG. 58 shows manufacturing process flows subsequent to a relocationwring forming process of a flip-chip type semiconductor integratedcircuit according to the present invention in the form of four types of(a), (b), (c) and (d). If the structure shown in FIG. 43 is taken as oneexample, then the manufacturing flows shown in the same drawing includerespective process steps: a relocation wiring forming S1 for formingeach relocation wiring 205 on an insulating layer 204, a surfaceinsulating layer forming S2 for forming such an insulating layer asdesignated at numeral 206, an under bump metallurgy forming S3 forforming such an under bump metallurgy as designated at numeral 207 andan under metallurgy 297 for each testing pad 209, etc., a functionselecting S4 like mode stetting based on the program for the antifuse 1,a probe testing S5, a defect relieving S6 like defective-bit replacementbased on the program for the antifuse 1, a bump forming S7 for formingeach bump electrode, a piece cutting (dicing) S8 for cutting out chipsfrom a wafer, a burn-in S9, and a final testing S10.

The manufacturing flow shown in FIG. 58(a) corresponds to the burn-inS9, i.e., a manufacturing flow for performing a continuous operationtest at a high temperature in chip units after the completion of thepiece cutting S8. Since the interval between solder bump electrodes ismade wider than the interval (of about 60 μm to about 150 μm) betweenbonding pads by each relocation wiring in the flip-chip typesemiconductor integrated circuit (about 0.5 mm to about 1.0 mm), theburn-in in each chip unit can easily be carried out through the use ofeach burn-in socket employed in a BGA (Ball Grid Array) type CSP (ChipSize Package). Namely, the bump electrodes are formed on the chip inadvance prior to the burn-in step, and arrangement patterns for the bumpelectrodes are respectively associated with electrode arrangementpatterns for the burn-in sockets. Thus it is not necessary to newlyprepare custom-engineered burn-in sockets. Therefore, the cost for theassembly of the flip-chip type semiconductor integrated circuit can bereduced. Even when the burn-in sockets with the bump electrodes used asconnecting terminals are not used, electrical connections for burn-incan be preformed by use of the testing pads 209. In this case,narrow-pitch type expensive burn-in probes capable of probing arenecessary for the testing pads placed between the bump electrodes,whereas the deformation of each solder bump electrode 208 due to socketcontact at a high temperature can be prevented.

In the manufacturing flows shown in FIGS. 58(b) and 58(c), the burn-inS9 are carried out in a wafer stage before the piece cutting S8. Inparticular, FIG. 58(b) is a manufacturing flow for performing burn-inbefore the formation of the solder bump electrodes by use of the testingpads 209 or the under bump metallurgies 207 antecedent to the formationof the solder bump electrodes 208. Since the electrical connections forburn-in are performed without having to use the bump electrodes, it ispossible to prevent the deformation of each solder bump electrode due tothe contact of each burn-in socket under a high-temperature environment.Further, since the burn-in is performed in a flat stage antecedent tothe formation of each solder bump electrode, a burn-in probe like asocket can easily be applied to each testing pad 209 without bringingthe solder bump electrodes 208 into obstacles. Since the burn-in is donein the wafer stage, a plurality of chips can be burnt in a lump andthroughput for testing can be improved.

FIG. 58(c) shows a manufacturing flow for performing burn-in after theformation of the solder bump electrodes. The burn-in probe is broughtinto contact with each solder bump electrode 208. When the burn-in probeis brought into contact with the solder bump electrode 208, the solderbump electrode 208 is easy to deform upon burn-in. However, there is inno danger of endamaging each under bump metallurgy 207 or developing asurface deterioration in the under bump metallurgy 207. It is alsopossible to form high-reliable under bump metallurgies and relocationwirings. Since the burn-in is performed in the wafer stage in the samemanner as FIG. 58(b) even in this case, throughput for testing can beimproved.

The manufacturing flow shown in FIG. 58(d) is a manufacturing flow inwhich the steps corresponding to the surface insulating layer forming S2in the respective flows shown in FIGS. 58(a) through 58(c) are replacedby a step corresponding to an under bump metallurgy forming S3. Processsteps subsequent to a function selecting step are common to any of themanufacturing flows shown in FIGS. 58(a) through 58(c). The relationshipbetween FIGS. 58(a) through 58(c) and FIG. 58(d) corresponds to therelationship between the structures shown in FIGS. 43 and 47 and thestructures shown in FIGS. 45 and 48. In the manufacturing flow shown inFIG. 58(d), the relocation wirings 205 and the under bump metallurgy 207are formed in the same step. Therefore, the forming cost of each underbump metallurgy can be reduced as compared with the manufacturing flowsshown in FIGS. 58(a) through 58(c).

Incidentally, when semiconductor integrated circuit elements aremanufactured in a fully-established process and percent defective islow, the burn-in might be omitted. In this case, the respectivemanufacturing flows shown in FIGS. 58(a) through 58(c) are preciselyidentical to one another and hence there is no difference.

FIG. 59 collectively shows chip contact points of a probe, a socket,etc. in respective testing processes of probe inspections S5, burn-in S9and final tests S10 in the above respective manufacturing process flows.In FIG. 59, terminals (pads) dedicated for probe testing are used onlyupon probe tests (including function selection, defect relief in a broadsense), and the probes are respectively brought into contact with thetesting pads described in the present invention.

In regard to power-supply and signal input/output terminals, the contactpoints at probe testing and burn-in differ according to the adoption ofany of the flows shown in FIGS. 58(a) through 58(c). However, any of thefinal tests is carried out by use of the solder bump electrodes ascompleted products.

In any of the respective manufacturing process flows shown in FIG. 58,the function selecting S4, the probe testing S5 and the defect relievingS6 are carried out in succession. When an antifuse is used in thefunction selecting S4 and the defect relieving S6, any of these threesteps can be performed by bringing each probe into contact with thewafer and thereby performing electrical processing (unaccompanied byfuse cut-out by laser and a change in relocation wiring). Therefore, thethree steps can be processed in a batch with one probing (i.e., withoutperforming probing again after probing on other chips), and hence theprocesses can be simplified. In this case, the function selection andthe defect relief can also be considered with being included in a broadprobe test.

In any of the respective manufacturing process flows shown in FIG. 58,the solder bump electrode forming S9 are collectively carried out in thewafer stage antecedent to the piece cutting S8 by the method or the likeshown in FIG. 56. Thus, the solder bump electrodes can be formedefficiently as compared with the conventional BGA and CSP manufacturingprocesses for forming the solder bump electrodes every piece chips.

Further, the execution of the three steps of the function selecting S4,probe testing S5 and defect relieving S6 prior to the solder bumpelectrode forming S7 makes it possible to easily perform probing withoutprotrusions from the solder bumps being taken as obstacles.

The function selecting S4 can also be carried out after the probetesting S5 and the defect relieving S6. However, if the functionselecting S4 is executed prior to the probe testing S5, then only apre-selected function may be tested upon the probe testing S5. It istherefore possible to reduce inspection items and improve inspectionefficiency.

The rate of demand between respective types obtained according to thefunction selecting S4 always changes according to the market situation.Thus, it is desirable to prepare stock in a state prior to the functionselection for the purpose of performing flexible support for the demandchange and minimizing the amount of stock every types. It is alsodesirable to cope with a step subsequent to the function selection in asshort periods as possible. Owing to the use of an antifuse for functionselection, the same relocation wiring patterns can be taken over all thetypes and the stock can be kept in a state placed immediately before theformation of each bump electrode. Thus, the required types can bemanufactured in a short period according to the change in demand, andthe amount of the stock can be reduced.

In regard to the manufacturing flows described in FIG. 58, the functionselecting S4 based on the program element can be performed after thebump electrode forming S7 contrary to the above. In this case, it isnecessary to expose electrodes for respectively applying voltages toprogram elements on the surface of a semiconductor integrated circuitfor the purpose of the function selection in a manner similar toprojecting or protruding electrodes. However, since each individualsemiconductor integrated circuits can be stocked in a state in which thewafer process has virtually been finished, except for a processattendant on the function selection, stock management is easy.

According to the flip-chip type semiconductor integrated circuit and itsmanufacturing method described above, the following operations andeffects can be obtained.

[1] Since program elements like antifuses 1 are adopted for flip-chiptype semiconductor integrated circuits 80 and 100, elicited degradationin reliability is not developed at all owing to the use of laser-fusiblefuses as the program elements.

If insulating films 204 and 206 are placed above and below a conductivelayer like the relocation wiring 205 where the conductive layer like therelocation wiring 205 is used as a relocation wiring for protrudingelectrodes 208 with respect to an arrangement of terminals like the pads202 a and 202 b, then the state of stress and distortion applied to asemiconductor substrate through each protruding electrode can berelaxed.

In the flip-chip type semiconductor integrated circuit, pad electrodes209 a and 209 b capable of being used for testing pads or the like forprobe tests can be exposed on the surface thereof. Some pad electrodes209 b lying in the pad electrodes can be used to apply voltages fordeveloping a predetermined potential difference in each program element.In the case of a circuit configuration (corresponding to the circuitcomprised of the transistors T9 through T11 shown in FIG. 22) in whichthe pad electrodes may be kept floating after the program element hasbeen programmed, the protruding electrodes 208 may not be assigned tothe pad electrodes 209 b. In doing so, the electrodes required toelectrically change the state of each program element employed in theflip-chip type semiconductor integrated circuit do not limit the numberof protruding electrodes for other applications. On the other hand, inthe case of a circuit configuration in which after the a program elementhas been programmed, pad electrodes must forcedly be set to a groundpotential Vss or a source voltage Vcc, protruding electrodes 208 areassigned to pad electrodes 209 b, and the protruding electrodes may beconnected to power wrings on a wiring board upon substrateimplementation.

If the electrode for applying the program voltage is shared between aplurality of program elements where the voltages for developing thepredetermined potential difference in the program element like theantifuse 1 are voltages different form normal operating source voltagesVss and Vcc employed in a circuit other than the program element as inthe case of Vbb′ and VDD, then the number of such external terminals canbe reduced.

Since a positive voltage VDD and a negative voltage Vbb′ are used tobreak down an insulating film for the antifuse 1, an absolutevalue-based voltage with a circuit's ground voltage Vss as the referencecan be limited to a substantially normal operating voltage when abreakdown potential difference for the antifuse 1 is obtained.

The program element like the antifuse 1 can be used for defectiverelief. Further, the program element can be used for function selectionof the semiconductor integrated circuit. Thus, the flip-chip typesemiconductor integrated circuit can easily obtain versatilityequivalent to a bonding option in terms of the function selection oroperation mode selection even after the formation of the protrudingelectrodes. The program element like the antifuse can also be adopted asmeans for storing trimming information used for selecting a circuit'scharacteristic.

[2] A method of manufacturing a semiconductor integrated circuit whereinprogram elements like antifuses 1 are adopted for a flip-chip typesemiconductor integrated circuit, includes, in addition to a first stepfor completing a wafer or the like having conventional bonding-wireconnecting bonding pads 202, for example, a second step S7 for forming aplurality of bump electrodes 208 for mounting connections, correspondingto some of the bonding pads 202, a third step S5 for testing orinspecting each circuit formed on the wafer, a fourth step S6 forreplacing a defective or faulty portion with a relieving circuitaccording to the result of inspection by the third step, a fifth step S9for performing burn-in, and a sixth step S8 for dicing the wafer.Further, the method includes a seventh step S4 for irreversibly changingthe state of each of the antifuses 1 to thereby select the function ofthe circuit. According to the above, the function selection of thesemiconductor integrated circuit is allowed without using a by-laserfusible fuse as a program element. Thus, this can contribute to yieldenhancement of a flip-chip type semiconductor integrated circuitsubjected to the function selection and manufactured, and an improvementin reliability thereof.

The function selection based on the program element can be carried outbefore the formation of the bump electrodes 208. Namely, the second stepS7 is carried out after the seventh step S4. After the formation of thebump electrodes 208, irregularities are formed on the wafer to no smallextent. If the function selection is done before the formation of thebump electrodes 208, then the contact of a probe with each pad orterminal for the application of a voltage to the antifuse 1 for functionselection is easy and the working efficiency of the function selectioncan be improved.

Contrary to the above, the function selecting S4 based on the antifuse 1can be performed after the formation of the bump electrodes 208 (S7). Inthis case, it is necessary to expose electrodes for respectivelyapplying voltages to antifuses 1 on the surface of a semiconductorintegrated circuit for the purpose of the function selection in a mannersimilar to the bump electrodes 208. However, since each individualsemiconductor integrated circuits can be stocked in a state in which thewafer process has virtually been finished, except for a processattendant on the function selection, stock management is easy.

In the fourth step S6 for replacing the defective portion by itscorresponding relieving circuit, the replacement can be performed whilethe state of each antifuse 1 is being irreversibly changed. At thistime, the respective steps corresponding to the function selecting S4,inspecting S5 and relieving S6 can be carried out by one circuit probingprocessing. Namely, the third step, fourth step and seventh step aresequentially performed and respectively include probing processing onthe terminals or bump electrodes 208 as needed. If the bump electrodes208 are formed after the respective steps corresponding to the functionselecting S4, inspecting S5 and relieving S6 (S7), then the contact of aprobe with each pad or terminal for the application of a voltage to eachantifuse is easy and the working efficiency of the inspection and reliefcan also be improved as well as that of the function selection.

If the bump electrodes 208 are formed according to the second step afterthe fifth step S9 for performing the burn-in (S7), it is thenunnecessary to consider the deformation of each protruding electrodeunder a high-temperature environment, and hence the burn-in can easilybe carried out from its standpoint.

[3] When attention is given to the replacement of a defective portionwith a relieving circuit in a flip-chip type semiconductor integratedcircuit, a method of manufacturing a semiconductor integrated circuitincludes, in addition to a first step for completing a wafer or the likehaving conventional bonding-wire connecting bonding pads 202, forexample, a second step S7 for forming a plurality of bump electrodes 208for mounting connections, corresponding to some of the bonding pads 202,a third step S5 for testing or inspecting each circuit formed on thewafer, a fourth step S6 for replacing a defective or faulty portion witha relieving circuit according to the result of inspection by the thirdstep, a fifth step S9 for performing burn-in, and a sixth step S8 fordicing the wafer. The fourth step S6 is provided as a step forirreversibly changing the state of each of the antifuses 1 to therebyperform the replacement. In the fourth step, a voltage for developing apredetermined potential difference is applied to the antifuse 1 througha predetermined terminal connected to the antifuse 1, of the pluralityof bonding pads 202. According to the above, the defective relief of thesemiconductor integrated circuit is allowed without using a by-laserfusible fuse as a program element. Thus, this can contribute to yieldenhancement of a flip-chip type semiconductor integrated circuitmanufactured under the relief, and an improvement in reliabilitythereof.

[4] When attention is given to a probe test for a flip-chip typesemiconductor integrated circuit, testing pads 209 b each using aconductive layer such as a relocation wiring layer 205 or an under bumpmetallurgy layer 297 or the like are provided just above or in theneighborhood of terminals 202 b like bonding pads, which are notprovided with bump electrodes thereat and are used only for probetesting. Namely, the testing pads 209 b are provided exclusively to thebump electrodes 208. Thus, the layout of the bump electrodes atpractical intervals can be facilitated to the fullest extent from themeaning of the mounting thereof to a circuit substrate.

Similar testing pads 209 a may be provided even with respect toterminals like bonding pads 202 a at which the bump electrodes 208 areprovided.

The probe test is executed by using these testing pads 209 a and 209 bor under the combined use of under bump metallurgies 207 antecedent tothe formation of the bump electrodes together with the testing pads 209b. According to the above, bump electrodes for pads dedicated for probetesting may not be added owing to the use of the testing pads 209 b.Owing to the addition of the testing pads 209 a even to the terminalshaving the bump electrodes 208, a wafer probe test can easily beperformed by using the testing pads 209 a and 209 b alone.

Further, the use of testing pads 209 a and 209 b provided in theneighborhood of the terminals like the bonding pads and smaller in sizethan the under bump metallurgies enables a probe test to be executedafter a relocation wiring process.

Conductive layers like relocation wirings 205, and testing pads areformed on an organic insulating layer 204 such as polyimide or the like.Owing to the provision of the testing pads on the organic insulatinglayer low in dielectric constant and easy to increase its thickness, thecapacitance between each of the testing pads and a semiconductor circuitplaced therebelow can be reduced. Since the modulus of elasticity of theorganic insulating layer is relatively low, the surface of each testingpad is easy to deform and hence contactability of each probe isenhanced.

Further, an insulating layer 206 is formed on the relocation wiring. Anunder bump metallurgy 207 and testing pads 209 b are formed thereon.Thus, the provision of each testing pad on the layered insulating layers204 and 206 corresponding to the two layers placed above and below therelocation wiring makes it possible to reduce the capacitance betweeneach testing pad and the semiconductor circuit placed therebelow.

[5] In a method of manufacturing a semiconductor integrated circuithaving a structure provided with the testing pads, burn-in is performedafter the execution of dicing posterior to the formation of bumpelectrodes. Alternatively, the bump electrodes are formed after burn-inin reverse and dicing may be carried out. In the former, burn-in socketsprepared for a BGA (Ball Grid Array) type semiconductor chip in whichexternal connecting electrodes are mapped in area array form, can beused appropriately in a manner similar to the flip-chip typesemiconductor integrated circuit. Alternatively, the arrangement of bumpelectrodes in area array form is matched with the arrangement of theterminals for the existing burn-in sockets, whereby custom-engineeredburn-in sockets may not be prepared newly and burn-in in each chip unitcan easily be performed. This also contributes even to a reduction intest cost. In the latter, the burn-in can also be carried out by usingtesting pads 209 a and 209 b or testing pads 209 b and an under bumpmetallurgy 207 as well as a probe test. Thus, contacting with eachsocket under a high temperature makes it possible to prevent thedeformation of protruding electrodes like solder bump electrodes.

While the invention made above by the present inventors has beendescribed specifically by the embodiments, the present invention is notlimited to the embodiments. It is needless to say that various changescan made thereto within the scope not departing from the substancethereof.

For example, means such as defective relief, function selection,trimming, etc. can be applied even to various memories such as an SRAM,an EEPROM, a flash memory, a programmable logic array using non-volatilestorage elements, etc. in addition to a DRAM and a synchronous DRAM, andvarious logic LSI such as a microcomputer, a microprocessor, etc.

A program element is not limited to an antifuse which undergoes anelectrical breakdown by a potential difference. Another electric fusemay be used which is molten by a potential difference so as to fall intoa high-resistance state. While the configuration using the selector 3 orthe like for the purpose of making an access decision to each reliefaddress for defective relief is shown as one example, various circuitconfigurations may be adopted. Similarly, the configuration of theantifuse circuit and the configuration of the address comparator canalso be changed in various ways. The function selection and the trimmingused as an alternative to the bonding option can also be applied toother applications.

The potential difference applied to the program element like theantifuse is not limited to the use of both a negative-polarity voltageand a positive-polarity voltage. Only the voltage having one polaritymay be used with a circuit's ground voltage as the reference.

Further, the terminal for inputting the negative voltage like Vbb′ isnot limited to the terminal dedicated for the fuse program. The inputterminal may share the use of a specific external terminal such as anaddress input terminal. As the shared terminal, the terminal functionlike the CGND is selected in a program mode, for example.

In the above description, the flip-chip type semiconductor integratedcircuit has been configured through the manufacturing process in whichthe relocation wirings, testing pads and bump electrodes are added tothe wire-bonding connecting wafer. The present invention is not limitedto such an idea and can undergo a process in which the manufacture ofthe flip-chip type semiconductor integrated circuit has been plannedfrom the beginning. In this case, bump electrodes like bonding pads maynot be provided. Terminals connected to conductive layers likerelocation wirings may be laid out.

As the electric fuse, the following ones may be used in addition to aconfiguration in which a resistance value at both ends (current path orchannel) of an electric fuse increases according to the application of apredetermined voltage to both ends thereof and a configuration in whichit decreases in reverse. Namely, the electric fuse may be comprised ofan element capable of reversibly holding information. For example, anEEPROM, an FRAM, a flash memory or the like may constitute the electricfuse. Alternatively, the electric fuse may be comprised of a one-timewritable ROM or EEPROM.

INDUSTRIAL APPLICABILITY

The present invention can widely be applied to various semiconductorintegrated circuits such as a DRAM or system LSI wherein a semiconductorsubstrate is provided with protruding electrodes such as solder bumpsfor the implementation of a circuit substrate.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: a semiconductor substrate; a plurality of circuit elementsformed in an element forming layer on said semiconductor substrate; aplurality of first and second terminals formed on the surface of saidelement forming layer and connected to predetermined ones of saidcircuit elements; a plurality of conductive layers which arerespectively connected to said first terminals and extending on saidelement forming layer; protruding electrodes respectively connected tosaid conductive layers; testing pads respectively connected to saidsecond terminals, said testing pads being not coupled to any protrudingelectrode; and an insulating film which covers the surfaces of saidprotruding electrodes and said testing pads so as to expose saidprotruding electrodes and said testing pads.
 2. A semiconductorintegrated circuit device comprising: a semiconductor substrate; aplurality of circuit elements formed in an element forming layer on saidsemiconductor substrate; first and second terminals formed on thesurface of said element forming layer and connected to predeterminedones of said circuit elements; a conductive layer which is connected tosaid first terminal; a protruding electrode connected to said conductivelayer; a testing pad connected to said second terminal, said testing padbeing not coupled to any protruding electrode; and an insulating filmwhich covers the surfaces of said protruding electrode and said testingpad so as to expose said protruding electrode and said testing pad. 3.The semiconductor integrated circuit device according to claim 1,wherein said conductive layers are metal wirings, said insulating filmis formed on said each metal wiring, and an insulating film is furtherformed below said each metal wiring.
 4. The semiconductor integratedcircuit device according to claim 3, wherein said insulating film andsaid further insulating film are respectively formed of differentmaterials, and said insulating film is formed of a material higher inelastic modulus than said further insulating film.
 5. The semiconductorintegrated circuit device according to claim 3, wherein said insulatingfilm is a film which contains an organic substance.
 6. The semiconductorintegrated circuit device according to claim 5, wherein the filmcontaining the organic substance is a polyimide film, a fluorocarbonresin film, or an elastomer film which contains a silicon or acrylicrubber material.
 7. The semiconductor integrated circuit deviceaccording to claim 1, wherein said testing pads are placed just abovesaid terminals corresponding thereto.
 8. The semiconductor integratedcircuit device according to claim 7, wherein said testing pads areregularly placed in the central portion of said semiconductor substrate,and said protruding electrodes are regularly placed outside said testingpads respectively.
 9. The semiconductor integrated circuit deviceaccording to claim 3, wherein said testing pads extend on said furtherinsulating film.
 10. A semiconductor integrated circuit devicecomprising: a semiconductor substrate; a first circuit element and asecond circuit element formed on said semiconductor substrate; a wiringformed over said semiconductor substrate and connected to said firstcircuit element; a bump formed over said wiring and connected thereto;and a conductive layer, which is formed over said semiconductorsubstrate and connected to said second circuit element and whichconstitutes a testing pad, wherein said conductive layer is electricallyisolated from any bump.
 11. A semiconductor integrated circuit devicecomprising: a semiconductor substrate; a semiconductor integratedcircuit element formed in said semiconductor substrate; a wiring formedon said semiconductor substrate and connected to said semiconductorintegrated circuit element; a bump formed on said wiring and connectedthereto; and a conductive layer, which is formed on said semiconductorsubstrate and connected to said semiconductor integrated circuit elementand which constitutes a testing pad which is electrically isolated fromany bump, wherein when said semiconductor integrated circuit element istested, said testing pad is electrically connected to the outside ofsaid semiconductor integrated circuit device, and when saidsemiconductor integrated circuit element is in normal operation, saidtesting pad is electrically disconnected from the outside of saidsemiconductor integrated circuit device.
 12. A semiconductor integratedcircuit device comprising: a semiconductor substrate; integrated circuitelements formed on said semiconductor substrate; a plurality of wiringsformed on said semiconductor substrate and connected to said integratedcircuit elements; a plurality of bumps formed on said plurality ofwirings and provided in association with said plurality of wirings; aconductive layer, which is formed on said semiconductor substrate andconnected to said integrated circuit elements and which is formed as atesting pad which is electrically isolated from any bump; and an organicfilm placed on said semiconductor substrate and formed below saidplurality of wirings, wherein when said each integrated circuit elementis tested, each said testing pad is electrically connected to theoutside of said semiconductor integrated circuit device, and when eachsaid integrated circuit element is in normal operation, each saidtesting pad is electrically disconnected from the outside of saidsemiconductor integrated circuit device.
 13. A semiconductor integratedcircuit device comprising: a semiconductor substrate; a first circuitelement and a second circuit element formed on said semiconductorsubstrate; a wiring formed on said semiconductor substrate and connectedto said first circuit element; a bump formed on said wiring andconnected thereto; a first conductive material, which is formed on saidsemiconductor substrate and connected to said first circuit element andwhich constitutes a first testing pad; and a second conductive material,which is formed on said semiconductor substrate and connected to saidsecond circuit element and which constitutes a second testing pad whichis not connected to any bump, wherein when said first circuit elementand said second circuit element are tested, said first testing pad andsaid second testing pad are electrically connected to the outside ofsaid semiconductor integrated circuit device, and when said firstcircuit element and said second circuit element are in normal operation,said first testing pad is electrically connected to the outside of saidsemiconductor integrated circuit device through said bump, and saidsecond testing pad is electrically disconnected from the outside of saidsemiconductor integrated circuit device.
 14. A semiconductor integratedcircuit device comprising: a semiconductor substrate; an integratedcircuit formed on said semiconductor substrate; a wiring formed on saidsemiconductor substrate and connected to said integrated circuit; a bumpformed on said wiring and connected thereto; a first conductive layer,which is formed on said semiconductor substrate and connected to saidintegrated circuit and which constitutes a first testing pad; and asecond conductive layer, which is formed on said semiconductor substrateand connected to said integrated circuit and which constitutes a secondtesting pad which is not connected to any bump, wherein said firstconductive layer and said wiring are connected to each other, and whensaid integrated circuit is tested, said first testing pad and saidsecond testing pad are electrically connected to the outside of saidsemiconductor integrated circuit device and when said integrated circuitis in normal operation, said first testing pad is electrically connectedto the outside of said semiconductor integrated circuit device and saidsecond testing pad is electrically isolated from the outside of saidsemiconductor integrated circuit device.
 15. A semiconductor integratedcircuit device comprising: a semiconductor substrate; integrated circuitelements formed on said semiconductor substrate; a plurality of wiringsformed over said semiconductor substrate and connected to at least oneof said integrated circuit elements; a plurality of bumps formed oversaid plurality of wirings and provided in association with saidplurality of wirings; a conductive layer, which is formed over saidsemiconductor substrate and connected to at least one of said integratedcircuit elements and which constitutes a test pad which is not connectedto any bump; and a film containing an organic material formed betweensaid semiconductor substrate and said plurality of wirings and betweensaid semiconductor substrate and said conductive layer, wherein whensaid integrated circuit element is tested, said test pad is electricallyconnected to the outside of said semiconductor integrated circuitdevice, and when said integrated circuit element is in normal operation,said test pad is electrically disconnected from the outside of saidsemiconductor integrated circuit device.